ENGR00222133 MX6SL - Fix crashes caused by Low power IDLE support

Need to ensure that the ARM_CLK rate stays exactly the same
when moving ARM_CLK from PLL2_PFD_400 to PLL1 when system
enters 24MHz state. Also need to ensure that PLL1 is enabled
before relocking the PLL to the correct rate.

Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>

diff --git a/arch/arm/mach-mx6/bus_freq.c b/arch/arm/mach-mx6/bus_freq.c
index 8c04e51d8827c7f6e8f201e94e9212e3988b3d03..23f56d5deaf14f65ed9c336771502d72086e4612 100644 (file)
--- a/arch/arm/mach-mx6/bus_freq.c
+++ b/arch/arm/mach-mx6/bus_freq.c
@@ -208,6 +208,10 @@ static void reduce_bus_freq_handler(struct work_struct *work)
                          * lowest possible freq.
                          */
                        org_arm_podf = __raw_readl(MXC_CCM_CACRR);
+                       /* Need to enable PLL1 before setting its rate. */
+                       clk_enable(pll1);
+                       clk_set_rate(pll1,
+                               cpu_op_tbl[cpu_op_nr - 1].pll_lpm_rate);
                        div = clk_get_rate(pll1) /
                                        cpu_op_tbl[cpu_op_nr - 1].cpu_rate;
 
@@ -308,6 +312,7 @@ int set_high_bus_freq(int high_bus_freq)
                        reg = __raw_writel(org_arm_podf, MXC_CCM_CACRR);
                        while (__raw_readl(MXC_CCM_CDHIPR))
                                ;
+                       clk_disable(pll1);
                }
                high_bus_freq_mode = 1;
                low_bus_freq_mode = 0;

diff --git a/arch/arm/mach-mx6/cpu_op-mx6.c b/arch/arm/mach-mx6/cpu_op-mx6.c
index 80e1c108963228a0c78f64a4e02f73ca3a26c3f8..7e054c1d743c8d7ae9dd50fb1783d5cf4d29d9cb 100644 (file)
--- a/arch/arm/mach-mx6/cpu_op-mx6.c
+++ b/arch/arm/mach-mx6/cpu_op-mx6.c
@@ -229,6 +229,7 @@ static struct cpu_op mx6sl_cpu_op_1G[] = {
         .cpu_voltage = 1200000,},
        {
         .pll_rate = 396000000,
+        .pll_lpm_rate = 792000000,
         .cpu_rate = 396000000,
         .cpu_podf = 0,
         .pu_voltage = 1050000,
@@ -236,6 +237,7 @@ static struct cpu_op mx6sl_cpu_op_1G[] = {
         .cpu_voltage = 1100000,},
         {
          .pll_rate = 396000000,
+        .pll_lpm_rate = 792000000,
          .cpu_rate = 198000000,
          .cpu_podf = 1,
          .pu_voltage = 1050000,
@@ -253,6 +255,7 @@ static struct cpu_op mx6sl_cpu_op[] = {
         .cpu_voltage = 1200000,},
         {
          .pll_rate = 396000000,
+        .pll_lpm_rate = 792000000,
          .cpu_rate = 396000000,
          .cpu_podf = 0,
         .pu_voltage = 1050000,
@@ -260,6 +263,7 @@ static struct cpu_op mx6sl_cpu_op[] = {
         .cpu_voltage = 1100000,},
        {
         .pll_rate = 396000000,
+        .pll_lpm_rate = 792000000,
         .cpu_rate = 198000000,
         .cpu_podf = 1,
          .pu_voltage = 1050000,

diff --git a/arch/arm/plat-mxc/include/mach/mxc.h b/arch/arm/plat-mxc/include/mach/mxc.h
index 3f58604f94dc2708781168b9630f4e726ea1f9ab..23159090ace8c00a60a182a2450cf613da7d98f9 100755 (executable)
--- a/arch/arm/plat-mxc/include/mach/mxc.h
+++ b/arch/arm/plat-mxc/include/mach/mxc.h
@@ -249,6 +249,7 @@ extern unsigned int __mxc_cpu_type;
 struct cpu_op {
        u32 pll_reg;
        u32 pll_rate;
+       u32 pll_lpm_rate;
        u32 cpu_rate;
        u32 pdr0_reg;
        u32 pdf;