ARM: tegra: fix comment in dsib clk set_parent

Since the clk framework has already taken necessary locks before calling
into the arch clk ops code, no further locks are needed while setting
the parent of dsib clk. This patch removes a comment that indicated
otherwise, and yet did not take any locks.

Signed-off-by: Sivaram Nair <sivaramn@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>

diff --git a/arch/arm/mach-tegra/tegra30_clocks.c b/arch/arm/mach-tegra/tegra30_clocks.c
index e9de5dfd94ec339e5f5c0c7c15eaad1f5a7944c4..c2102a312bc5b77c4475206aa3d49b90f927db2e 100644 (file)
--- a/arch/arm/mach-tegra/tegra30_clocks.c
+++ b/arch/arm/mach-tegra/tegra30_clocks.c
@@ -1913,9 +1913,7 @@ struct clk_ops tegra30_periph_clk_ops = {
 static int tegra30_dsib_clk_set_parent(struct clk_hw *hw, u8 index)
 {
        struct clk *d = clk_get_sys(NULL, "pll_d");
-       /* The DSIB parent selection bit is in PLLD base
-          register - can not do direct r-m-w, must be
-          protected by PLLD lock */
+       /* The DSIB parent selection bit is in PLLD base register */
        tegra_clk_cfg_ex(
                d, TEGRA_CLK_PLLD_MIPI_MUX_SEL, index);