- Fix GPIO_16 IOMUX config.
- Config GPIO_16 pad to ENET_ANATOP_ETHERNET_REF_OUT.
- IEEE-1588 ts_clk, S/PDIF in and i2c3 are mutually exclusive,
because all of them use GPIO_16, so it only for one function
work at a moment.
- Test result:
Enet work fine at 100/1000Mbps in TO1.1.
IEEE 1588 timestamp is convergent.
Signed-off-by: Fugang Duan <B38611@freescale.com>
MX6DL_PAD_RGMII_RD2__ENET_RGMII_RD2,
MX6DL_PAD_RGMII_RD3__ENET_RGMII_RD3,
MX6DL_PAD_RGMII_RX_CTL__ENET_RGMII_RX_CTL,
+#ifdef CONFIG_FEC_1588
+ MX6DL_PAD_GPIO_16__ENET_ANATOP_ETHERNET_REF_OUT,
+#endif
#endif
/* MCLK for csi0 */
MX6DL_PAD_GPIO_0__CCM_CLKO,
}
/*
- * S/PDIF in and i2c3 are mutually exclusive because both
- * use GPIO_16.
+ * IEEE-1588 ts_clk, S/PDIF in and i2c3 are mutually exclusive
+ * because all of them use GPIO_16.
* S/PDIF out and can1 stby are mutually exclusive because both
* use GPIO_17.
*/
+#ifndef CONFIG_FEC_1588
if (spdif_en) {
BUG_ON(!spdif_pads);
mxc_iomux_v3_setup_multiple_pads(spdif_pads, spdif_pads_cnt);
BUG_ON(!i2c3_pads);
mxc_iomux_v3_setup_multiple_pads(i2c3_pads, i2c3_pads_cnt);
}
+#else
+ /* Set GPIO_16 input for IEEE-1588 ts_clk and RMII reference clock
+ * For MX6 GPR1 bit21 meaning:
+ * Bit21: 0 - GPIO_16 pad output
+ * 1 - GPIO_16 pad input
+ */
+ mxc_iomux_set_gpr_register(1, 21, 1, 1);
+#endif
if (!spdif_en && flexcan_en) {
BUG_ON(!flexcan_pads);
MX6Q_PAD_RGMII_RD2__ENET_RGMII_RD2,
MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3,
MX6Q_PAD_RGMII_RX_CTL__ENET_RGMII_RX_CTL,
+#ifdef CONFIG_FEC_1588
+ MX6Q_PAD_GPIO_16__ENET_ANATOP_ETHERNET_REF_OUT,
+#endif
#endif
/* MCLK for csi0 */
MX6Q_PAD_GPIO_0__CCM_CLKO,
/* Enable ENET ref clock */
reg = __raw_readl(PLL8_ENET_BASE_ADDR);
reg &= ~ANADIG_PLL_BYPASS;
- reg &= ~ANADIG_PLL_ENABLE;
+ reg |= ANADIG_PLL_ENABLE;
__raw_writel(reg, PLL8_ENET_BASE_ADDR);
_clk_enable(clk);
/* Enable ENET ref clock */
reg = __raw_readl(PLL8_ENET_BASE_ADDR);
reg |= ANADIG_PLL_BYPASS;
- reg |= ANADIG_PLL_ENABLE;
+ reg &= ~ANADIG_PLL_ENABLE;
__raw_writel(reg, PLL8_ENET_BASE_ADDR);
}
#define MX6DL_PAD_GPIO_16__ENET_1588_EVENT2_IN \
IOMUX_PAD(0x05E4, 0x0214, 1, 0x0000, 0, NO_PAD_CTRL)
#define MX6DL_PAD_GPIO_16__ENET_ANATOP_ETHERNET_REF_OUT \
- IOMUX_PAD(0x05E4, 0x0214, 2, 0x080C, 0, NO_PAD_CTRL)
+ IOMUX_PAD(0x05E4, 0x0214, 0x12, 0x080C, 0, NO_PAD_CTRL)
#define MX6DL_PAD_GPIO_16__USDHC1_LCTL \
IOMUX_PAD(0x05E4, 0x0214, 3, 0x0000, 0, MX6DL_USDHC_PAD_CTRL)
#define MX6DL_PAD_GPIO_16__SPDIF_IN1 \
#define _MX6Q_PAD_GPIO_16__ENET_1588_EVENT2_IN \
IOMUX_PAD(0x0618, 0x0248, 1, 0x0000, 0, 0)
#define _MX6Q_PAD_GPIO_16__ENET_ANATOP_ETHERNET_REF_OUT \
- IOMUX_PAD(0x0618, 0x0248, 2, 0x083C, 1, 0)
+ IOMUX_PAD(0x0618, 0x0248, 0x12, 0x083C, 1, 0)
#define _MX6Q_PAD_GPIO_16__USDHC1_LCTL \
IOMUX_PAD(0x0618, 0x0248, 3, 0x0000, 0, 0)
#define _MX6Q_PAD_GPIO_16__SPDIF_IN1 \