#define MX6Q_PAD_NANDF_CS0__USBOH3_UH2_DFD_OUT_15 \
(_MX6Q_PAD_NANDF_CS0__USBOH3_UH2_DFD_OUT_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX6Q_PAD_NANDF_CS0__GPIO_6_11 \
- (_MX6Q_PAD_NANDF_CS0__GPIO_6_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
+ (_MX6Q_PAD_NANDF_CS0__GPIO_6_11 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
#define MX6Q_PAD_NANDF_CS0__PL301_MX6QPER1_HSIZE_2 \
(_MX6Q_PAD_NANDF_CS0__PL301_MX6QPER1_HSIZE_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX6Q_PAD_NANDF_CS1__PCIE_CTRL_DIAG_STATUS_BUS_MUX_3 \
(_MX6Q_PAD_NANDF_CS1__PCIE_CTRL_DIAG_STATUS_BUS_MUX_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX6Q_PAD_NANDF_CS1__GPIO_6_14 \
- (_MX6Q_PAD_NANDF_CS1__GPIO_6_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
+ (_MX6Q_PAD_NANDF_CS1__GPIO_6_14 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
#define MX6Q_PAD_NANDF_CS1__PL301_MX6QPER1_HREADYOUT \
(_MX6Q_PAD_NANDF_CS1__PL301_MX6QPER1_HREADYOUT | MUX_PAD_CTRL(NO_PAD_CTRL))