ENGR00277654 imx: pcie: enable pcie lm errata when pcie is enabled

Enable the SW workaround of the PCIe lower power errata
only when PCIe is enabled. Otherwise, don't apply the
SW workaround.

Signed-off-by: Richard Zhu <r65037@freescale.com>

diff --git a/arch/arm/mach-imx/pm-imx6.c b/arch/arm/mach-imx/pm-imx6.c
index ea1643f925e3b88c98262973dbf5583fa9aef0ca..dc638a5339483730b3432f11414515bef90b769b 100644 (file)
--- a/arch/arm/mach-imx/pm-imx6.c
+++ b/arch/arm/mach-imx/pm-imx6.c
@@ -218,7 +218,7 @@ static int imx6_suspend_finish(unsigned long val)
 
 static int imx6_pm_enter(suspend_state_t state)
 {
-       struct regmap *gpr;
+       struct regmap *g;
 
        /*
         * L2 can exit by 'reset' or Inband beacon (from remote EP)
@@ -226,13 +226,15 @@ static int imx6_pm_enter(suspend_state_t state)
         * So, toggle bit18 of GPR1, to fix errata
         * "PCIe PCIe does not support L2 Power Down"
         */
-       gpr = syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr");
-       if (IS_ERR(gpr)) {
-               pr_err("failed to find fsl,imx6q-iomux-gpr regmap\n");
-               return PTR_ERR(gpr);
+       if (IS_ENABLED(CONFIG_PCIE_IMX)) {
+               g = syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr");
+               if (IS_ERR(g)) {
+                       pr_err("failed to find fsl,imx6q-iomux-gpr regmap\n");
+                       return PTR_ERR(g);
+               }
+               regmap_update_bits(g, IOMUXC_GPR1, IMX6Q_GPR1_PCIE_TEST_PD,
+                               IMX6Q_GPR1_PCIE_TEST_PD);
        }
-       regmap_update_bits(gpr, IOMUXC_GPR1, IMX6Q_GPR1_PCIE_TEST_PD,
-                       IMX6Q_GPR1_PCIE_TEST_PD);
 
        switch (state) {
        case PM_SUSPEND_STANDBY:
@@ -272,8 +274,10 @@ static int imx6_pm_enter(suspend_state_t state)
         * So, toggle bit18 of GPR1, to fix errata
         * "PCIe PCIe does not support L2 Power Down"
         */
-       regmap_update_bits(gpr, IOMUXC_GPR1, IMX6Q_GPR1_PCIE_TEST_PD,
-                       !IMX6Q_GPR1_PCIE_TEST_PD);
+       if (IS_ENABLED(CONFIG_PCIE_IMX)) {
+               regmap_update_bits(g, IOMUXC_GPR1, IMX6Q_GPR1_PCIE_TEST_PD,
+                               !IMX6Q_GPR1_PCIE_TEST_PD);
+       }
 
        return 0;
 }