#define BINTEN 0x8 /* GPIO Interrupt Per-Bank Enable Register */
-#define chip2controller(chip) \
- container_of(chip, struct davinci_gpio_controller, chip)
-
static void __iomem *gpio_base;
static struct davinci_gpio_regs __iomem *gpio2regs(unsigned gpio)
static inline int __davinci_direction(struct gpio_chip *chip,
unsigned offset, bool out, int value)
{
- struct davinci_gpio_controller *d = chip2controller(chip);
+ struct davinci_gpio_controller *d = gpiochip_get_data(chip);
struct davinci_gpio_regs __iomem *g = d->regs;
unsigned long flags;
u32 temp;
*/
static int davinci_gpio_get(struct gpio_chip *chip, unsigned offset)
{
- struct davinci_gpio_controller *d = chip2controller(chip);
+ struct davinci_gpio_controller *d = gpiochip_get_data(chip);
struct davinci_gpio_regs __iomem *g = d->regs;
return !!((1 << offset) & readl_relaxed(&g->in_data));
static void
davinci_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
{
- struct davinci_gpio_controller *d = chip2controller(chip);
+ struct davinci_gpio_controller *d = gpiochip_get_data(chip);
struct davinci_gpio_regs __iomem *g = d->regs;
writel_relaxed((1 << offset), value ? &g->set_data : &g->clr_data);
chips[i].clr_data = ®s->clr_data;
chips[i].in_data = ®s->in_data;
- gpiochip_add(&chips[i].chip);
+ gpiochip_add_data(&chips[i].chip, &chips[i]);
}
platform_set_drvdata(pdev, chips);
static int gpio_to_irq_banked(struct gpio_chip *chip, unsigned offset)
{
- struct davinci_gpio_controller *d = chip2controller(chip);
+ struct davinci_gpio_controller *d = gpiochip_get_data(chip);
if (d->irq_domain)
return irq_create_mapping(d->irq_domain, d->chip.base + offset);
static int gpio_to_irq_unbanked(struct gpio_chip *chip, unsigned offset)
{
- struct davinci_gpio_controller *d = chip2controller(chip);
+ struct davinci_gpio_controller *d = gpiochip_get_data(chip);
/*
* NOTE: we assume for now that only irqs in the first gpio_chip