]> git.karo-electronics.de Git - karo-tx-linux.git/commitdiff
ARM64: dts: meson-gxl-p23x: Enable ethernet
authorNeil Armstrong <narmstrong@baylibre.com>
Mon, 7 Nov 2016 10:43:56 +0000 (11:43 +0100)
committerKevin Hilman <khilman@baylibre.com>
Tue, 15 Nov 2016 20:05:49 +0000 (12:05 -0800)
Enable Ethernet on the p23x board, pinctrl attribute is only added for
the p230 board since the p231 only uses the Internal PHY.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p230.dts
arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p231.dts
arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p23x.dtsi

index 3dfaa37f78f4118ad68d4e29cc34579136f923e9..4d082a7fdf510b48c314bf8972d1a40e6eff4bab 100644 (file)
        compatible = "amlogic,p230", "amlogic,s905d", "amlogic,meson-gxl";
        model = "Amlogic Meson GXL (S905D) P230 Development Board";
 };
+
+/* P230 has exclusive choice between internal or external PHY */
+&ethmac {
+       pinctrl-0 = <&eth_pins>;
+       pinctrl-names = "default";
+
+       /* Select external PHY by default */
+       phy-handle = <&external_phy>;
+
+       /* External PHY reset is shared with internal PHY Led signals */
+       snps,reset-gpio = <&gpio GPIOZ_14 0>;
+       snps,reset-delays-us = <0 10000 1000000>;
+       snps,reset-active-low;
+
+       /* External PHY is in RGMII */
+       phy-mode = "rgmii";
+};
+
+&external_mdio {
+       external_phy: ethernet-phy@0 {
+               compatible = "ethernet-phy-id001c.c916", "ethernet-phy-ieee802.3-c22";
+               reg = <0>;
+               max-speed = <1000>;
+       };
+};
index ade8d29e5477e916e9c176a5a842a8b69f73c0b8..1cc8d49d85e4135e36acc042d5bcdb27dcd50ff7 100644 (file)
@@ -49,3 +49,9 @@
        compatible = "amlogic,p231", "amlogic,s905d", "amlogic,meson-gxl";
        model = "Amlogic Meson GXL (S905D) P231 Development Board";
 };
+
+/* P231 has only internal PHY port */
+&ethmac {
+       phy-mode = "rmii";
+       phy-handle = <&internal_phy>;
+};
index bbe46a2b7f14ca1e1627e0913fc48cd8677b7594..622ffbeba33688fb900269a1a179d9711db0bb3a 100644 (file)
        clocks = <&clkc CLKID_FCLK_DIV4>;
        clock-names = "clkin0";
 };
+
+&ethmac {
+       status = "okay";
+};