.get_max_clock = sdhci_pltfm_clk_get_max_clock,
};
+static struct sdhci_pltfm_data sdhci_pxav3_pdata = {
+ .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL
+ | SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC
+ | SDHCI_QUIRK_32BIT_ADMA_SIZE
+ | SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
+ .ops = &pxav3_sdhci_ops,
+};
+
#ifdef CONFIG_OF
static const struct of_device_id sdhci_pxav3_of_match[] = {
{
if (!pxa)
return -ENOMEM;
- host = sdhci_pltfm_init(pdev, NULL);
+ host = sdhci_pltfm_init(pdev, &sdhci_pxav3_pdata);
if (IS_ERR(host)) {
kfree(pxa);
return PTR_ERR(host);
pltfm_host->clk = clk;
clk_prepare_enable(clk);
- host->quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL
- | SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC
- | SDHCI_QUIRK_32BIT_ADMA_SIZE
- | SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN;
-
/* enable 1/8V DDR capable */
host->mmc->caps |= MMC_CAP_1_8V_DDR;
}
}
- host->ops = &pxav3_sdhci_ops;
-
sdhci_get_of_property(pdev);
pm_runtime_set_active(&pdev->dev);