PCI: rockchip: Unindent rockchip_pcie_set_power_limit()

If regulator_get_current_limit() returns 0 or error, return early so the
body of the function doesn't have to be indented as the body of an "if"
statement.  No functional change intended.

Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>

diff --git a/drivers/pci/host/pcie-rockchip.c b/drivers/pci/host/pcie-rockchip.c
index d785f64ec03b68950dc6e5c34f983b2716b30fbc..7f76ff6af0bac13aa413d68725ac4030fe839e14 100644 (file)
--- a/drivers/pci/host/pcie-rockchip.c
+++ b/drivers/pci/host/pcie-rockchip.c
@@ -438,24 +438,25 @@ static void rockchip_pcie_set_power_limit(struct rockchip_pcie *rockchip)
         * to the actual power supply.
         */
        curr = regulator_get_current_limit(rockchip->vpcie3v3);
-       if (curr > 0) {
-               scale = 3; /* 0.001x */
-               curr = curr / 1000; /* convert to mA */
-               power = (curr * 3300) / 1000; /* milliwatt */
-               while (power > PCIE_RC_CONFIG_DCR_CSPL_LIMIT) {
-                       if (!scale) {
-                               dev_warn(rockchip->dev, "invalid power supply\n");
-                               return;
-                       }
-                       scale--;
-                       power = power / 10;
-               }
+       if (curr <= 0)
+               return;
 
-               status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_DCR);
-               status |= (power << PCIE_RC_CONFIG_DCR_CSPL_SHIFT) |
-                         (scale << PCIE_RC_CONFIG_DCR_CPLS_SHIFT);
-               rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_DCR);
+       scale = 3; /* 0.001x */
+       curr = curr / 1000; /* convert to mA */
+       power = (curr * 3300) / 1000; /* milliwatt */
+       while (power > PCIE_RC_CONFIG_DCR_CSPL_LIMIT) {
+               if (!scale) {
+                       dev_warn(rockchip->dev, "invalid power supply\n");
+                       return;
+               }
+               scale--;
+               power = power / 10;
        }
+
+       status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_DCR);
+       status |= (power << PCIE_RC_CONFIG_DCR_CSPL_SHIFT) |
+                 (scale << PCIE_RC_CONFIG_DCR_CPLS_SHIFT);
+       rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_DCR);
 }
 
 /**