{
__iomem void *base;
int i, reg;
+ u32 parent_rate, rate;
+ unsigned long ipg_clk_rate, max_arm_wait_clk;
external_low_reference = ckil;
external_high_reference = ckih1;
lp_med_freq = 0;
lp_audio_freq = 0;
+ /* Get current ARM_PODF value */
+ rate = clk_get_rate(&cpu_clk);
+ parent_rate = clk_get_rate(&pll1_sw_clk);
+ cur_arm_podf = parent_rate / rate;
+
+ /* Calculate the ARM_PODF to be applied when the system
+ * enters WAIT state.
+ * The max ARM clk is decided by the ipg_clk and has to
+ * follow the ratio of ARM_CLK:IPG_CLK of 12:5.
+ */
+ ipg_clk_rate = clk_get_rate(&ipg_clk);
+ max_arm_wait_clk = (12 * ipg_clk_rate) / 5;
+ wait_mode_arm_podf = parent_rate / max_arm_wait_clk;
+
/* Turn OFF all unnecessary PHYs. */
if (cpu_is_mx6q()) {
/* Turn off SATA PHY. */
unsigned long ckih1, unsigned long ckih2)
{
int i;
+ u32 parent_rate, rate;
+ unsigned long ipg_clk_rate, max_arm_wait_clk;
external_low_reference = ckil;
external_high_reference = ckih1;
lp_high_freq = 0;
lp_med_freq = 0;
+ /* Get current ARM_PODF value */
+ rate = clk_get_rate(&cpu_clk);
+ parent_rate = clk_get_rate(&pll1_sw_clk);
+ cur_arm_podf = parent_rate / rate;
+
+ /* Calculate the ARM_PODF to be applied when the system
+ * enters WAIT state.
+ * The max ARM clk is decided by the ipg_clk and has to
+ * follow the ratio of ARM_CLK:IPG_CLK of 12:5.
+ */
+ ipg_clk_rate = clk_get_rate(&ipg_clk);
+ max_arm_wait_clk = (12 * ipg_clk_rate) / 5;
+ wait_mode_arm_podf = parent_rate / max_arm_wait_clk;
+
return 0;
}
static void __iomem *gpc_base = IO_ADDRESS(GPC_BASE_ADDR);
-int wait_mode_arm_podf;
volatile unsigned int num_cpu_idle;
volatile unsigned int num_cpu_idle_lock = 0x0;
int wait_mode_arm_podf;