clk: tegra: Micro-optimize Tegra210 clock setup

sor_safe being the parent of the dpaux and dpaux1 clocks, it's not only
natural, but also slightly more efficient, to initialize it before its
children. This avoids orphaning the dpaux and dpaux1 clocks only to get
them reparented when the sor_safe clock is registered.

Acked-by: Jon Hunter <jonathanh@nvidia.com>
Tested-by: Jon Hunter <jonathanh@nvidia.com>
Acked-by: Rhyland Klein <rklein@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

diff --git a/drivers/clk/tegra/clk-tegra210.c b/drivers/clk/tegra/clk-tegra210.c
index fe295b4102caa47bb31166fadceade5f91eced61..b4df5c46642f0c4d051af10196987a797b0811e7 100644 (file)
--- a/drivers/clk/tegra/clk-tegra210.c
+++ b/drivers/clk/tegra/clk-tegra210.c
@@ -2466,6 +2466,10 @@ static __init void tegra210_periph_clk_init(void __iomem *clk_base,
                                        1, 2);
        clks[TEGRA210_CLK_XUSB_SS_DIV2] = clk;
 
+       clk = tegra_clk_register_periph_fixed("sor_safe", "pll_p", 0, clk_base,
+                                             1, 17, 222);
+       clks[TEGRA210_CLK_SOR_SAFE] = clk;
+
        clk = tegra_clk_register_periph_fixed("dpaux", "sor_safe", 0, clk_base,
                                              1, 17, 181);
        clks[TEGRA210_CLK_DPAUX] = clk;
@@ -2474,10 +2478,6 @@ static __init void tegra210_periph_clk_init(void __iomem *clk_base,
                                              1, 17, 207);
        clks[TEGRA210_CLK_DPAUX1] = clk;
 
-       clk = tegra_clk_register_periph_fixed("sor_safe", "pll_p", 0, clk_base,
-                                             1, 17, 222);
-       clks[TEGRA210_CLK_SOR_SAFE] = clk;
-
        /* pll_d_dsi_out */
        clk = clk_register_gate(NULL, "pll_d_dsi_out", "pll_d_out0", 0,
                                clk_base + PLLD_MISC0, 21, 0, &pll_d_lock);