Merge git://git.denx.de/u-boot-dm

diff --git a/arch/arc/Kconfig b/arch/arc/Kconfig
index a8dc4e2336da12aeef0c696be61267688492d925..24f5c02c760544cfaac9e50a8a3cc6946bda94b7 100644 (file)
--- a/arch/arc/Kconfig
+++ b/arch/arc/Kconfig
@@ -8,30 +8,79 @@ config USE_PRIVATE_LIBGCC
        default y
 
 config SYS_CPU
-       default "arcv1"
+       default "arcv1" if ISA_ARCOMPACT
+       default "arcv2" if ISA_ARCV2
+
+choice
+       prompt "ARC Instruction Set"
+       default ISA_ARCOMPACT
+
+config ISA_ARCOMPACT
+       bool "ARCompact ISA"
+       help
+         The original ARC ISA of ARC600/700 cores
+
+config ISA_ARCV2
+       bool "ARC ISA v2"
+       help
+         ISA for the Next Generation ARC-HS cores
+
+endchoice
 
 choice
        prompt "CPU selection"
-       default CPU_ARC770D
+       default CPU_ARC770D if ISA_ARCOMPACT
+       default CPU_ARCHS38 if ISA_ARCV2
 
 config CPU_ARC750D
        bool "ARC 750D"
        select ARC_MMU_V2
+       depends on ISA_ARCOMPACT
        help
          Choose this option to build an U-Boot for ARC750D CPU.
 
 config CPU_ARC770D
        bool "ARC 770D"
        select ARC_MMU_V3
+       depends on ISA_ARCOMPACT
        help
          Choose this option to build an U-Boot for ARC770D CPU.
 
+config CPU_ARCEM6
+       bool "ARC EM6"
+       select ARC_MMU_ABSENT
+       depends on ISA_ARCV2
+       help
+         Next Generation ARC Core based on ISA-v2 ISA without MMU.
+
+config CPU_ARCHS36
+       bool "ARC HS36"
+       select ARC_MMU_ABSENT
+       depends on ISA_ARCV2
+       help
+         Next Generation ARC Core based on ISA-v2 ISA without MMU.
+
+config CPU_ARCHS38
+       bool "ARC HS38"
+       select ARC_MMU_V4
+       depends on ISA_ARCV2
+       help
+         Next Generation ARC Core based on ISA-v2 ISA with MMU.
+
 endchoice
 
 choice
        prompt "MMU Version"
        default ARC_MMU_V3 if CPU_ARC770D
        default ARC_MMU_V2 if CPU_ARC750D
+       default ARC_MMU_ABSENT if CPU_ARCEM6
+       default ARC_MMU_ABSENT if CPU_ARCHS36
+       default ARC_MMU_V4 if CPU_ARCHS38
+
+config ARC_MMU_ABSENT
+       bool "No MMU"
+       help
+         No MMU
 
 config ARC_MMU_V2
        bool "MMU v2"
@@ -48,6 +97,12 @@ config ARC_MMU_V3
          Variable Page size (1k-16k), var JTLB size 128 x (2 or 4)
          Shared Address Spaces (SASID)
 
+config ARC_MMU_V4
+       bool "MMU v4"
+       depends on CPU_ARCHS38
+       help
+         Introduced as a part of ARC HS38 release.
+
 endchoice
 
 config CPU_BIG_ENDIAN

diff --git a/arch/arc/config.mk b/arch/arc/config.mk
index f1e81b689502e94126c74d78c6c6bfa670e5478b..4fcd4076c460de18b39fce0dd233d16bfcba1fb0 100644 (file)
--- a/arch/arc/config.mk
+++ b/arch/arc/config.mk
@@ -38,6 +38,18 @@ ifdef CONFIG_CPU_ARC770D
 PLATFORM_CPPFLAGS += -marc700 -mlock -mswape
 endif
 
+ifdef CONFIG_CPU_ARCEM6
+PLATFORM_CPPFLAGS += -marcem
+endif
+
+ifdef CONFIG_CPU_ARCHS34
+PLATFORM_CPPFLAGS += -marchs
+endif
+
+ifdef CONFIG_CPU_ARCHS38
+PLATFORM_CPPFLAGS += -marchs
+endif
+
 PLATFORM_CPPFLAGS += -ffixed-r25 -D__ARC__ -gdwarf-2
 
 # Needed for relocation

diff --git a/arch/arc/cpu/arcv2/Makefile b/arch/arc/cpu/arcv2/Makefile
new file mode 100644 (file)
index 0000000..cc69e5a
--- /dev/null
+++ b/arch/arc/cpu/arcv2/Makefile
@@ -0,0 +1,7 @@
+#
+# Copyright (C) 2013-2015 Synopsys, Inc. All rights reserved.
+#
+# SPDX-License-Identifier:     GPL-2.0+
+#
+
+obj-y += start.o

diff --git a/arch/arc/cpu/arcv2/start.S b/arch/arc/cpu/arcv2/start.S
new file mode 100644 (file)
index 0000000..3ce6896
--- /dev/null
+++ b/arch/arc/cpu/arcv2/start.S
@@ -0,0 +1,254 @@
+/*
+ * Copyright (C) 2013-2015 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <asm-offsets.h>
+#include <config.h>
+#include <asm/arcregs.h>
+
+/*
+ * Note on the LD/ST addressing modes with address register write-back
+ *
+ * LD.a same as LD.aw
+ *
+ * LD.a    reg1, [reg2, x]  => Pre Incr
+ *      Eff Addr for load = [reg2 + x]
+ *
+ * LD.ab   reg1, [reg2, x]  => Post Incr
+ *      Eff Addr for load = [reg2]
+ */
+
+.macro PUSH reg
+       st.a    \reg, [%sp, -4]
+.endm
+
+.macro PUSHAX aux
+       lr      %r9, [\aux]
+       PUSH    %r9
+.endm
+
+.macro  SAVE_R1_TO_R24
+       PUSH    %r1
+       PUSH    %r2
+       PUSH    %r3
+       PUSH    %r4
+       PUSH    %r5
+       PUSH    %r6
+       PUSH    %r7
+       PUSH    %r8
+       PUSH    %r9
+       PUSH    %r10
+       PUSH    %r11
+       PUSH    %r12
+       PUSH    %r13
+       PUSH    %r14
+       PUSH    %r15
+       PUSH    %r16
+       PUSH    %r17
+       PUSH    %r18
+       PUSH    %r19
+       PUSH    %r20
+       PUSH    %r21
+       PUSH    %r22
+       PUSH    %r23
+       PUSH    %r24
+.endm
+
+.macro SAVE_ALL_SYS
+       /* saving %r0 to reg->r0 in advance since weread %ecr into it */
+       st      %r0, [%sp, -8]
+       lr      %r0, [%ecr]     /* all stack addressing is manual so far */
+       st      %r0, [%sp]
+       st      %sp, [%sp, -4]
+       /* now move %sp to reg->r0 position so we can do "push" automatically */
+       sub     %sp, %sp, 8
+
+       SAVE_R1_TO_R24
+       PUSH    %r25
+       PUSH    %gp
+       PUSH    %fp
+       PUSH    %blink
+       PUSHAX  %eret
+       PUSHAX  %erstatus
+       PUSH    %lp_count
+       PUSHAX  %lp_end
+       PUSHAX  %lp_start
+       PUSHAX  %erbta
+.endm
+
+.macro SAVE_EXCEPTION_SOURCE
+#ifdef CONFIG_MMU
+       /* If MMU exists exception faulting address is loaded in EFA reg */
+       lr      %r0, [%efa]
+#else
+       /* Otherwise in ERET (exception return) reg */
+       lr      %r0, [%eret]
+#endif
+.endm
+
+.section .ivt, "a",@progbits
+.align 4
+       /* Critical system events */
+.word  _start                  /* 0 - 0x000 */
+.word  memory_error            /* 1 - 0x008 */
+.word  instruction_error       /* 2 - 0x010 */
+
+       /* Exceptions */
+.word  EV_MachineCheck         /* 0x100, Fatal Machine check  (0x20) */
+.word  EV_TLBMissI             /* 0x108, Intruction TLB miss  (0x21) */
+.word  EV_TLBMissD             /* 0x110, Data TLB miss        (0x22) */
+.word  EV_TLBProtV             /* 0x118, Protection Violation (0x23)
+                                                       or Misaligned Access  */
+.word  EV_PrivilegeV           /* 0x120, Privilege Violation  (0x24) */
+.word  EV_Trap                 /* 0x128, Trap exception       (0x25) */
+.word  EV_Extension            /* 0x130, Extn Intruction Excp (0x26) */
+
+       /* Device interrupts */
+.rept  29
+       j       interrupt_handler       /* 3:31 - 0x018:0xF8 */
+.endr
+
+.text
+.globl _start
+_start:
+       /* Setup interrupt vector base that matches "__text_start" */
+       sr      __ivt_start, [ARC_AUX_INTR_VEC_BASE]
+
+       /* Setup stack pointer */
+       mov     %sp, CONFIG_SYS_INIT_SP_ADDR
+       mov     %fp, %sp
+
+       /* Clear bss */
+       mov     %r0, __bss_start
+       mov     %r1, __bss_end
+
+clear_bss:
+       st.ab   0, [%r0, 4]
+       brlt    %r0, %r1, clear_bss
+
+       /* Zero the one and only argument of "board_init_f" */
+       mov_s   %r0, 0
+       j       board_init_f
+
+memory_error:
+       SAVE_ALL_SYS
+       SAVE_EXCEPTION_SOURCE
+       mov     %r1, %sp
+       j       do_memory_error
+
+instruction_error:
+       SAVE_ALL_SYS
+       SAVE_EXCEPTION_SOURCE
+       mov     %r1, %sp
+       j       do_instruction_error
+
+interrupt_handler:
+       /* Todo - save and restore CPU context when interrupts will be in use */
+       bl      do_interrupt_handler
+       rtie
+
+EV_MachineCheck:
+       SAVE_ALL_SYS
+       SAVE_EXCEPTION_SOURCE
+       mov     %r1, %sp
+       j       do_machine_check_fault
+
+EV_TLBMissI:
+       SAVE_ALL_SYS
+       mov     %r0, %sp
+       j       do_itlb_miss
+
+EV_TLBMissD:
+       SAVE_ALL_SYS
+       mov     %r0, %sp
+       j       do_dtlb_miss
+
+EV_TLBProtV:
+       SAVE_ALL_SYS
+       SAVE_EXCEPTION_SOURCE
+       mov     %r1, %sp
+       j       do_tlb_prot_violation
+
+EV_PrivilegeV:
+       SAVE_ALL_SYS
+       mov     %r0, %sp
+       j       do_privilege_violation
+
+EV_Trap:
+       SAVE_ALL_SYS
+       mov     %r0, %sp
+       j       do_trap
+
+EV_Extension:
+       SAVE_ALL_SYS
+       mov     %r0, %sp
+       j       do_extension
+
+/*
+ * void relocate_code (addr_sp, gd, addr_moni)
+ *
+ * This "function" does not return, instead it continues in RAM
+ * after relocating the monitor code.
+ *
+ * r0 = start_addr_sp
+ * r1 = new__gd
+ * r2 = relocaddr
+ */
+.align 4
+.globl relocate_code
+relocate_code:
+       /*
+        * r0-r12 might be clobbered by C functions
+        * so we use r13-r16 for storage here
+        */
+       mov     %r13, %r0               /* save addr_sp */
+       mov     %r14, %r1               /* save addr of gd */
+       mov     %r15, %r2               /* save addr of destination */
+
+       mov     %r16, %r2               /* %r9 - relocation offset */
+       sub     %r16, %r16, __image_copy_start
+
+/* Set up the stack */
+stack_setup:
+       mov     %sp, %r13
+       mov     %fp, %sp
+
+/* Check if monitor is loaded right in place for relocation */
+       mov     %r0, __image_copy_start
+       cmp     %r0, %r15               /* skip relocation if code loaded */
+       bz      do_board_init_r         /* in target location already */
+
+/* Copy data (__image_copy_start - __image_copy_end) to new location */
+       mov     %r1, %r15
+       mov     %r2, __image_copy_end
+       sub     %r2, %r2, %r0           /* r3 <- amount of bytes to copy */
+       asr     %r2, %r2, 2             /* r3 <- amount of words to copy */
+       mov     %lp_count, %r2
+       lp      copy_end
+       ld.ab   %r2,[%r0,4]
+       st.ab   %r2,[%r1,4]
+copy_end:
+
+/* Fix relocations related issues */
+       bl      do_elf_reloc_fixups
+#ifndef CONFIG_SYS_ICACHE_OFF
+       bl      invalidate_icache_all
+#endif
+#ifndef CONFIG_SYS_DCACHE_OFF
+       bl      flush_dcache_all
+#endif
+
+/* Update position of intterupt vector table */
+       lr      %r0, [ARC_AUX_INTR_VEC_BASE]    /* Read current position */
+       add     %r0, %r0, %r16                  /* Update address */
+       sr      %r0, [ARC_AUX_INTR_VEC_BASE]    /* Write new position */
+
+do_board_init_r:
+/* Prepare for exection of "board_init_r" in relocated monitor */
+       mov     %r2, board_init_r       /* old address of "board_init_r()" */
+       add     %r2, %r2, %r16          /* new address of "board_init_r()" */
+       mov     %r0, %r14               /* 1-st parameter: gd_t */
+       mov     %r1, %r15               /* 2-nd parameter: dest_addr */
+       j       [%r2]

diff --git a/arch/arc/include/asm/cache.h b/arch/arc/include/asm/cache.h
index 27259612217265ae950ec165dc34fab310657ab8..8a77cd93af2c1d317e7813e83a2e154233ead8eb 100644 (file)
--- a/arch/arc/include/asm/cache.h
+++ b/arch/arc/include/asm/cache.h
@@ -17,10 +17,14 @@
 #define ARCH_DMA_MINALIGN              128
 #endif
 
-#if defined(CONFIG_ARC_MMU_V2)
+#if defined(ARC_MMU_ABSENT)
+#define CONFIG_ARC_MMU_VER 0
+#elif defined(CONFIG_ARC_MMU_V2)
 #define CONFIG_ARC_MMU_VER 2
 #elif defined(CONFIG_ARC_MMU_V3)
 #define CONFIG_ARC_MMU_VER 3
+#elif defined(CONFIG_ARC_MMU_V4)
+#define CONFIG_ARC_MMU_VER 4
 #endif
 
 #endif /* __ASM_ARC_CACHE_H */

diff --git a/arch/arm/cpu/armv7/rmobile/Kconfig b/arch/arm/cpu/armv7/rmobile/Kconfig
index 6d94199de854f3f0bec29a5fee642b63a53b5e54..35866508a38b23b38bf8ab191f309dd1b3aba6c7 100644 (file)
--- a/arch/arm/cpu/armv7/rmobile/Kconfig
+++ b/arch/arm/cpu/armv7/rmobile/Kconfig
@@ -21,6 +21,9 @@ config TARGET_KZM9G
 config TARGET_ALT
        bool "Alt board"
 
+config TARGET_SILK
+       bool "Silk board"
+
 endchoice
 
 config SYS_SOC
@@ -28,7 +31,7 @@ config SYS_SOC
 
 config RMOBILE_EXTRAM_BOOT
        bool "Enable boot from RAM"
-       depends on TARGET_ALT || TARGET_KOELSCH || TARGET_LAGER
+       depends on TARGET_ALT || TARGET_KOELSCH || TARGET_LAGER || TARGET_SILK
        default n
 
 source "board/atmark-techno/armadillo-800eva/Kconfig"
@@ -37,5 +40,6 @@ source "board/renesas/koelsch/Kconfig"
 source "board/renesas/lager/Kconfig"
 source "board/kmc/kzm9g/Kconfig"
 source "board/renesas/alt/Kconfig"
+source "board/renesas/silk/Kconfig"
 
 endif

diff --git a/arch/arm/cpu/armv7/rmobile/lowlevel_init_ca15.S b/arch/arm/cpu/armv7/rmobile/lowlevel_init_ca15.S
index d47546a11d7ad61def4ec26e2ca27171698c71ad..a5dbbea9e1527d79f26348d939735408bd65e4ef 100644 (file)
--- a/arch/arm/cpu/armv7/rmobile/lowlevel_init_ca15.S
+++ b/arch/arm/cpu/armv7/rmobile/lowlevel_init_ca15.S
@@ -40,7 +40,7 @@ do_lowlevel_init:
        and     r1, r1, #0x7F00
        lsrs    r1, r1, #8
        cmp     r1, #0x4C               /* 0x4C is ID of r8a7794 */
-       beq     _exit_init_l2_a15
+       beq     _enable_actlr_smp
 
        /* surpress wfe if ca15 */
        tst r4, #4
@@ -64,6 +64,16 @@ do_lowlevel_init:
        orrne r0, r0, #0x20             /* L2CTLR[5] */
 #endif
        mcrne p15, 1, r0, c9, c0, 2
+
+       b       _exit_init_l2_a15
+
+_enable_actlr_smp: /* R8A7794 only (CA7) */
+#ifndef CONFIG_DCACHE_OFF
+       mrc    p15, 0, r0, c1, c0, 1
+       orr    r0, r0, #0x40
+       mcr    p15, 0, r0, c1, c0, 1
+#endif
+
 _exit_init_l2_a15:
        ldr     r3, =(CONFIG_SYS_INIT_SP_ADDR)
        sub     sp, r3, #4

diff --git a/board/renesas/silk/Kconfig b/board/renesas/silk/Kconfig
new file mode 100644 (file)
index 0000000..07aee0e
--- /dev/null
+++ b/board/renesas/silk/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_SILK
+
+config SYS_BOARD
+       default "silk"
+
+config SYS_VENDOR
+       default "renesas"
+
+config SYS_CONFIG_NAME
+       default "silk"
+
+endif

diff --git a/board/renesas/silk/MAINTAINERS b/board/renesas/silk/MAINTAINERS
new file mode 100644 (file)
index 0000000..b566ccf
--- /dev/null
+++ b/board/renesas/silk/MAINTAINERS
@@ -0,0 +1,6 @@
+SILK BOARD
+M:     Cogent Embedded, Inc. <source@cogentembedded.com>
+S:     Maintained
+F:     board/renesas/silk/
+F:     include/configs/silk.h
+F:     configs/silk_defconfig

diff --git a/board/renesas/silk/Makefile b/board/renesas/silk/Makefile
new file mode 100644 (file)
index 0000000..e6eea61
--- /dev/null
+++ b/board/renesas/silk/Makefile
@@ -0,0 +1,10 @@
+#
+# board/renesas/silk/Makefile
+#
+# Copyright (C) 2015 Renesas Electronics Corporation
+# Copyright (C) 2015 Cogent Embedded, Inc.
+#
+# SPDX-License-Identifier: GPL-2.0
+#
+
+obj-y  := silk.o qos.o ../rcar-gen2-common/common.o

diff --git a/board/renesas/silk/qos.c b/board/renesas/silk/qos.c
new file mode 100644 (file)
index 0000000..4f6e46c
--- /dev/null
+++ b/board/renesas/silk/qos.c
@@ -0,0 +1,951 @@
+/*
+ * board/renesas/silk/qos.c
+ *
+ * Copyright (C) 2015 Renesas Electronics Corporation
+ * Copyright (C) 2015 Cogent Embedded, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ *
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <asm/mach-types.h>
+#include <asm/io.h>
+#include <asm/arch/rmobile.h>
+
+#if defined(CONFIG_RMOBILE_EXTRAM_BOOT)
+/* QoS version 0.11 */
+
+enum {
+       DBSC3_00, DBSC3_01, DBSC3_02, DBSC3_03, DBSC3_04,
+       DBSC3_05, DBSC3_06, DBSC3_07, DBSC3_08, DBSC3_09,
+       DBSC3_10, DBSC3_11, DBSC3_12, DBSC3_13, DBSC3_14,
+       DBSC3_15,
+       DBSC3_NR,
+};
+
+static u32 dbsc3_0_r_qos_addr[DBSC3_NR] = {
+       [DBSC3_00] = DBSC3_0_QOS_R0_BASE,
+       [DBSC3_01] = DBSC3_0_QOS_R1_BASE,
+       [DBSC3_02] = DBSC3_0_QOS_R2_BASE,
+       [DBSC3_03] = DBSC3_0_QOS_R3_BASE,
+       [DBSC3_04] = DBSC3_0_QOS_R4_BASE,
+       [DBSC3_05] = DBSC3_0_QOS_R5_BASE,
+       [DBSC3_06] = DBSC3_0_QOS_R6_BASE,
+       [DBSC3_07] = DBSC3_0_QOS_R7_BASE,
+       [DBSC3_08] = DBSC3_0_QOS_R8_BASE,
+       [DBSC3_09] = DBSC3_0_QOS_R9_BASE,
+       [DBSC3_10] = DBSC3_0_QOS_R10_BASE,
+       [DBSC3_11] = DBSC3_0_QOS_R11_BASE,
+       [DBSC3_12] = DBSC3_0_QOS_R12_BASE,
+       [DBSC3_13] = DBSC3_0_QOS_R13_BASE,
+       [DBSC3_14] = DBSC3_0_QOS_R14_BASE,
+       [DBSC3_15] = DBSC3_0_QOS_R15_BASE,
+};
+
+static u32 dbsc3_0_w_qos_addr[DBSC3_NR] = {
+       [DBSC3_00] = DBSC3_0_QOS_W0_BASE,
+       [DBSC3_01] = DBSC3_0_QOS_W1_BASE,
+       [DBSC3_02] = DBSC3_0_QOS_W2_BASE,
+       [DBSC3_03] = DBSC3_0_QOS_W3_BASE,
+       [DBSC3_04] = DBSC3_0_QOS_W4_BASE,
+       [DBSC3_05] = DBSC3_0_QOS_W5_BASE,
+       [DBSC3_06] = DBSC3_0_QOS_W6_BASE,
+       [DBSC3_07] = DBSC3_0_QOS_W7_BASE,
+       [DBSC3_08] = DBSC3_0_QOS_W8_BASE,
+       [DBSC3_09] = DBSC3_0_QOS_W9_BASE,
+       [DBSC3_10] = DBSC3_0_QOS_W10_BASE,
+       [DBSC3_11] = DBSC3_0_QOS_W11_BASE,
+       [DBSC3_12] = DBSC3_0_QOS_W12_BASE,
+       [DBSC3_13] = DBSC3_0_QOS_W13_BASE,
+       [DBSC3_14] = DBSC3_0_QOS_W14_BASE,
+       [DBSC3_15] = DBSC3_0_QOS_W15_BASE,
+};
+
+void qos_init(void)
+{
+       int i;
+       struct rcar_s3c *s3c;
+       struct rcar_s3c_qos *s3c_qos;
+       struct rcar_dbsc3_qos *qos_addr;
+       struct rcar_mxi *mxi;
+       struct rcar_mxi_qos *mxi_qos;
+       struct rcar_axi_qos *axi_qos;
+
+       /* DBSC DBADJ2 */
+       writel(0x20042004, DBSC3_0_DBADJ2);
+
+       /* S3C -QoS */
+       s3c = (struct rcar_s3c *)S3C_BASE;
+       writel(0x1F0D0B0A, &s3c->s3crorr);
+       writel(0x1F0D0B09, &s3c->s3cworr);
+
+       /* QoS Control Registers */
+       s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_CCI0_BASE;
+       writel(0x00890089, &s3c_qos->s3cqos0);
+       writel(0x20960010, &s3c_qos->s3cqos1);
+       writel(0x20302030, &s3c_qos->s3cqos2);
+       writel(0x20AA2200, &s3c_qos->s3cqos3);
+       writel(0x00002032, &s3c_qos->s3cqos4);
+       writel(0x20960010, &s3c_qos->s3cqos5);
+       writel(0x20302030, &s3c_qos->s3cqos6);
+       writel(0x20AA2200, &s3c_qos->s3cqos7);
+       writel(0x00002032, &s3c_qos->s3cqos8);
+
+       s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_CCI1_BASE;
+       writel(0x00890089, &s3c_qos->s3cqos0);
+       writel(0x20960010, &s3c_qos->s3cqos1);
+       writel(0x20302030, &s3c_qos->s3cqos2);
+       writel(0x20AA2200, &s3c_qos->s3cqos3);
+       writel(0x00002032, &s3c_qos->s3cqos4);
+       writel(0x20960010, &s3c_qos->s3cqos5);
+       writel(0x20302030, &s3c_qos->s3cqos6);
+       writel(0x20AA2200, &s3c_qos->s3cqos7);
+       writel(0x00002032, &s3c_qos->s3cqos8);
+
+       s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_MXI_BASE;
+       writel(0x80928092, &s3c_qos->s3cqos0);
+       writel(0x20960020, &s3c_qos->s3cqos1);
+       writel(0x20302030, &s3c_qos->s3cqos2);
+       writel(0x20AA20DC, &s3c_qos->s3cqos3);
+       writel(0x00002032, &s3c_qos->s3cqos4);
+       writel(0x20960020, &s3c_qos->s3cqos5);
+       writel(0x20302030, &s3c_qos->s3cqos6);
+       writel(0x20AA20DC, &s3c_qos->s3cqos7);
+       writel(0x00002032, &s3c_qos->s3cqos8);
+
+       s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_AXI_BASE;
+       writel(0x00820082, &s3c_qos->s3cqos0);
+       writel(0x20960020, &s3c_qos->s3cqos1);
+       writel(0x20302030, &s3c_qos->s3cqos2);
+       writel(0x20AA20FA, &s3c_qos->s3cqos3);
+       writel(0x00002032, &s3c_qos->s3cqos4);
+       writel(0x20960020, &s3c_qos->s3cqos5);
+       writel(0x20302030, &s3c_qos->s3cqos6);
+       writel(0x20AA20FA, &s3c_qos->s3cqos7);
+       writel(0x00002032, &s3c_qos->s3cqos8);
+
+       /* DBSC -QoS */
+       /* DBSC0 - Read */
+       for (i = DBSC3_00; i < DBSC3_NR; i++) {
+               qos_addr = (struct rcar_dbsc3_qos *)dbsc3_0_r_qos_addr[i];
+               writel(0x00000002, &qos_addr->dblgcnt);
+               writel(0x0000207D, &qos_addr->dbtmval0);
+               writel(0x00002053, &qos_addr->dbtmval1);
+               writel(0x0000202A, &qos_addr->dbtmval2);
+               writel(0x00001FBD, &qos_addr->dbtmval3);
+               writel(0x00000001, &qos_addr->dbrqctr);
+               writel(0x00002064, &qos_addr->dbthres0);
+               writel(0x0000203E, &qos_addr->dbthres1);
+               writel(0x00002019, &qos_addr->dbthres2);
+               writel(0x00000001, &qos_addr->dblgqon);
+       }
+
+       /* DBSC0 - Write */
+       for (i = DBSC3_00; i < DBSC3_NR; i++) {
+               qos_addr = (struct rcar_dbsc3_qos *)dbsc3_0_w_qos_addr[i];
+               writel(0x00000002, &qos_addr->dblgcnt);
+               writel(0x0000207D, &qos_addr->dbtmval0);
+               writel(0x00002053, &qos_addr->dbtmval1);
+               writel(0x00002043, &qos_addr->dbtmval2);
+               writel(0x00002030, &qos_addr->dbtmval3);
+               writel(0x00000001, &qos_addr->dbrqctr);
+               writel(0x00002064, &qos_addr->dbthres0);
+               writel(0x0000203E, &qos_addr->dbthres1);
+               writel(0x00002031, &qos_addr->dbthres2);
+               writel(0x00000001, &qos_addr->dblgqon);
+       }
+
+       /* CCI-400 -QoS */
+       writel(0x20000800, CCI_400_MAXOT_1);
+       writel(0x20000800, CCI_400_MAXOT_2);
+       writel(0x0000000C, CCI_400_QOSCNTL_1);
+       writel(0x0000000C, CCI_400_QOSCNTL_2);
+
+       /* MXI -QoS */
+       /* Transaction Control (MXI) */
+       mxi = (struct rcar_mxi *)MXI_BASE;
+       writel(0x00000013, &mxi->mxrtcr);
+       writel(0x00000013, &mxi->mxwtcr);
+       writel(0x00780080, &mxi->mxsaar0);
+       writel(0x02000800, &mxi->mxsaar1);
+
+       /* QoS Control (MXI) */
+       mxi_qos = (struct rcar_mxi_qos *)MXI_QOS_BASE;
+       writel(0x0000000C, &mxi_qos->vspdu0);
+       writel(0x0000000E, &mxi_qos->du0);
+
+       /* AXI -QoS */
+       /* Transaction Control (MXI) */
+       axi_qos = (struct rcar_axi_qos *)SYS_AXI_SYX64TO128_BASE;
+       writel(0x00000002, &axi_qos->qosconf);
+       writel(0x00002245, &axi_qos->qosctset0);
+       writel(0x00002096, &axi_qos->qosctset1);
+       writel(0x00002030, &axi_qos->qosctset2);
+       writel(0x00002030, &axi_qos->qosctset3);
+       writel(0x00000001, &axi_qos->qosreqctr);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00000000, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)SYS_AXI_AVB_BASE;
+       writel(0x00000000, &axi_qos->qosconf);
+       writel(0x000020A6, &axi_qos->qosctset0);
+       writel(0x00000001, &axi_qos->qosreqctr);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00000000, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMUX0_BASE;
+       writel(0x00000002, &axi_qos->qosconf);
+       writel(0x00002245, &axi_qos->qosctset0);
+       writel(0x00002096, &axi_qos->qosctset1);
+       writel(0x00002030, &axi_qos->qosctset2);
+       writel(0x00002030, &axi_qos->qosctset3);
+       writel(0x00000001, &axi_qos->qosreqctr);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00000000, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMUX1_BASE;
+       writel(0x00000002, &axi_qos->qosconf);
+       writel(0x00002245, &axi_qos->qosctset0);
+       writel(0x00002096, &axi_qos->qosctset1);
+       writel(0x00002030, &axi_qos->qosctset2);
+       writel(0x00002030, &axi_qos->qosctset3);
+       writel(0x00000001, &axi_qos->qosreqctr);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00000000, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMUX2_BASE;
+       writel(0x00000002, &axi_qos->qosconf);
+       writel(0x00002245, &axi_qos->qosctset0);
+       writel(0x00002096, &axi_qos->qosctset1);
+       writel(0x00002030, &axi_qos->qosctset2);
+       writel(0x00002030, &axi_qos->qosctset3);
+       writel(0x00000001, &axi_qos->qosreqctr);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00000000, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)SYS_AXI_LBS_BASE;
+       writel(0x00000000, &axi_qos->qosconf);
+       writel(0x0000214C, &axi_qos->qosctset0);
+       writel(0x00000001, &axi_qos->qosreqctr);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00000000, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUDS_BASE;
+       writel(0x00000001, &axi_qos->qosconf);
+       writel(0x00002004, &axi_qos->qosctset0);
+       writel(0x00002096, &axi_qos->qosctset1);
+       writel(0x00002030, &axi_qos->qosctset2);
+       writel(0x00002030, &axi_qos->qosctset3);
+       writel(0x00000001, &axi_qos->qosreqctr);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00000000, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUM_BASE;
+       writel(0x00000001, &axi_qos->qosconf);
+       writel(0x00002004, &axi_qos->qosctset0);
+       writel(0x00002096, &axi_qos->qosctset1);
+       writel(0x00002030, &axi_qos->qosctset2);
+       writel(0x00002030, &axi_qos->qosctset3);
+       writel(0x00000001, &axi_qos->qosreqctr);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00000000, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUS0_BASE;
+       writel(0x00000001, &axi_qos->qosconf);
+       writel(0x00002004, &axi_qos->qosctset0);
+       writel(0x00002096, &axi_qos->qosctset1);
+       writel(0x00002030, &axi_qos->qosctset2);
+       writel(0x00002030, &axi_qos->qosctset3);
+       writel(0x00000001, &axi_qos->qosreqctr);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00000000, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUS1_BASE;
+       writel(0x00000001, &axi_qos->qosconf);
+       writel(0x00002004, &axi_qos->qosctset0);
+       writel(0x00002096, &axi_qos->qosctset1);
+       writel(0x00002030, &axi_qos->qosctset2);
+       writel(0x00002030, &axi_qos->qosctset3);
+       writel(0x00000001, &axi_qos->qosreqctr);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00000000, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)SYS_AXI_RTX_BASE;
+       writel(0x00000002, &axi_qos->qosconf);
+       writel(0x00002245, &axi_qos->qosctset0);
+       writel(0x00002096, &axi_qos->qosctset1);
+       writel(0x00002030, &axi_qos->qosctset2);
+       writel(0x00002030, &axi_qos->qosctset3);
+       writel(0x00000001, &axi_qos->qosreqctr);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00000000, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDS0_BASE;
+       writel(0x00000000, &axi_qos->qosconf);
+       writel(0x000020A6, &axi_qos->qosctset0);
+       writel(0x00000001, &axi_qos->qosreqctr);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00000000, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDS1_BASE;
+       writel(0x00000000, &axi_qos->qosconf);
+       writel(0x000020A6, &axi_qos->qosctset0);
+       writel(0x00000001, &axi_qos->qosreqctr);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00000000, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)SYS_AXI_USB20_BASE;
+       writel(0x00000000, &axi_qos->qosconf);
+       writel(0x00002053, &axi_qos->qosctset0);
+       writel(0x00000001, &axi_qos->qosreqctr);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00000000, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)SYS_AXI_USB22_BASE;
+       writel(0x00000000, &axi_qos->qosconf);
+       writel(0x00002053, &axi_qos->qosctset0);
+       writel(0x00000001, &axi_qos->qosreqctr);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00000000, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)SYS_AXI_AX2M_BASE;
+       writel(0x00000002, &axi_qos->qosconf);
+       writel(0x00002245, &axi_qos->qosctset0);
+       writel(0x00000001, &axi_qos->qosreqctr);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00000000, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)SYS_AXI_CC50_BASE;
+       writel(0x00000000, &axi_qos->qosconf);
+       writel(0x00002029, &axi_qos->qosctset0);
+       writel(0x00000001, &axi_qos->qosreqctr);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00000000, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)SYS_AXI_CCI_BASE;
+       writel(0x00000002, &axi_qos->qosconf);
+       writel(0x00002245, &axi_qos->qosctset0);
+       writel(0x00000001, &axi_qos->qosreqctr);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00000000, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)SYS_AXI_CS_BASE;
+       writel(0x00000000, &axi_qos->qosconf);
+       writel(0x00002053, &axi_qos->qosctset0);
+       writel(0x00000001, &axi_qos->qosreqctr);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00000000, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)SYS_AXI_DDM_BASE;
+       writel(0x00000000, &axi_qos->qosconf);
+       writel(0x000020A6, &axi_qos->qosctset0);
+       writel(0x00000001, &axi_qos->qosreqctr);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00000000, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)SYS_AXI_ETH_BASE;
+       writel(0x00000000, &axi_qos->qosconf);
+       writel(0x00002053, &axi_qos->qosctset0);
+       writel(0x00000001, &axi_qos->qosreqctr);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00000000, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)SYS_AXI_MPXM_BASE;
+       writel(0x00000002, &axi_qos->qosconf);
+       writel(0x00002245, &axi_qos->qosctset0);
+       writel(0x00000001, &axi_qos->qosreqctr);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00000000, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDM0_BASE;
+       writel(0x00000000, &axi_qos->qosconf);
+       writel(0x0000214C, &axi_qos->qosctset0);
+       writel(0x00000001, &axi_qos->qosreqctr);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00000000, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDM1_BASE;
+       writel(0x00000000, &axi_qos->qosconf);
+       writel(0x0000214C, &axi_qos->qosctset0);
+       writel(0x00000001, &axi_qos->qosreqctr);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00000000, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)SYS_AXI_TRAB_BASE;
+       writel(0x00000000, &axi_qos->qosconf);
+       writel(0x000020A6, &axi_qos->qosctset0);
+       writel(0x00000001, &axi_qos->qosreqctr);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00000000, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)SYS_AXI_UDM0_BASE;
+       writel(0x00000000, &axi_qos->qosconf);
+       writel(0x00002053, &axi_qos->qosctset0);
+       writel(0x00000001, &axi_qos->qosreqctr);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00000000, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)SYS_AXI_UDM1_BASE;
+       writel(0x00000000, &axi_qos->qosconf);
+       writel(0x00002053, &axi_qos->qosctset0);
+       writel(0x00000001, &axi_qos->qosreqctr);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00000000, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       /* QoS Register (RT-AXI) */
+       axi_qos = (struct rcar_axi_qos *)RT_AXI_SHX_BASE;
+       writel(0x00000000, &axi_qos->qosconf);
+       writel(0x00002053, &axi_qos->qosctset0);
+       writel(0x00002096, &axi_qos->qosctset1);
+       writel(0x00002030, &axi_qos->qosctset2);
+       writel(0x00002030, &axi_qos->qosctset3);
+       writel(0x00000001, &axi_qos->qosreqctr);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00000000, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)RT_AXI_DBG_BASE;
+       writel(0x00000000, &axi_qos->qosconf);
+       writel(0x00002053, &axi_qos->qosctset0);
+       writel(0x00002096, &axi_qos->qosctset1);
+       writel(0x00002030, &axi_qos->qosctset2);
+       writel(0x00002030, &axi_qos->qosctset3);
+       writel(0x00000001, &axi_qos->qosreqctr);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00000000, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)RT_AXI_RTX64TO128_BASE;
+       writel(0x00000002, &axi_qos->qosconf);
+       writel(0x00002245, &axi_qos->qosctset0);
+       writel(0x00002096, &axi_qos->qosctset1);
+       writel(0x00002030, &axi_qos->qosctset2);
+       writel(0x00002030, &axi_qos->qosctset3);
+       writel(0x00000001, &axi_qos->qosreqctr);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00000000, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)RT_AXI_SY2RT_BASE;
+       writel(0x00000002, &axi_qos->qosconf);
+       writel(0x00002245, &axi_qos->qosctset0);
+       writel(0x00000001, &axi_qos->qosreqctr);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00000000, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       /* QoS Register (MP-AXI) */
+       axi_qos = (struct rcar_axi_qos *)MP_AXI_ADSP_BASE;
+       writel(0x00000000, &axi_qos->qosconf);
+       writel(0x00002037, &axi_qos->qosctset0);
+       writel(0x00000001, &axi_qos->qosreqctr);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00000000, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)MP_AXI_ASDS0_BASE;
+       writel(0x00000001, &axi_qos->qosconf);
+       writel(0x00002014, &axi_qos->qosctset0);
+       writel(0x00000040, &axi_qos->qosreqctr);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00000000, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)MP_AXI_ASDS1_BASE;
+       writel(0x00000001, &axi_qos->qosconf);
+       writel(0x00002014, &axi_qos->qosctset0);
+       writel(0x00000040, &axi_qos->qosreqctr);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00000000, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)MP_AXI_MLP_BASE;
+       writel(0x00000001, &axi_qos->qosconf);
+       writel(0x00001FF0, &axi_qos->qosctset0);
+       writel(0x00000020, &axi_qos->qosreqctr);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00002001, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)MP_AXI_MMUMP_BASE;
+       writel(0x00000001, &axi_qos->qosconf);
+       writel(0x00002004, &axi_qos->qosctset0);
+       writel(0x00002096, &axi_qos->qosctset1);
+       writel(0x00002030, &axi_qos->qosctset2);
+       writel(0x00002030, &axi_qos->qosctset3);
+       writel(0x00000001, &axi_qos->qosreqctr);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00000000, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)MP_AXI_SPU_BASE;
+       writel(0x00000000, &axi_qos->qosconf);
+       writel(0x00002053, &axi_qos->qosctset0);
+       writel(0x00000001, &axi_qos->qosreqctr);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00000000, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)MP_AXI_SPUC_BASE;
+       writel(0x00000000, &axi_qos->qosconf);
+       writel(0x0000206E, &axi_qos->qosctset0);
+       writel(0x00000001, &axi_qos->qosreqctr);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00000000, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       /* QoS Register (SYS-AXI256) */
+       axi_qos = (struct rcar_axi_qos *)SYS_AXI256_AXI128TO256_BASE;
+       writel(0x00000002, &axi_qos->qosconf);
+       writel(0x000020EB, &axi_qos->qosctset0);
+       writel(0x00002096, &axi_qos->qosctset1);
+       writel(0x00002030, &axi_qos->qosctset2);
+       writel(0x00002030, &axi_qos->qosctset3);
+       writel(0x00000001, &axi_qos->qosreqctr);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00000000, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)SYS_AXI256_SYX_BASE;
+       writel(0x00000002, &axi_qos->qosconf);
+       writel(0x000020EB, &axi_qos->qosctset0);
+       writel(0x00002096, &axi_qos->qosctset1);
+       writel(0x00002030, &axi_qos->qosctset2);
+       writel(0x00002030, &axi_qos->qosctset3);
+       writel(0x00000001, &axi_qos->qosreqctr);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00000000, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)SYS_AXI256_MPX_BASE;
+       writel(0x00000002, &axi_qos->qosconf);
+       writel(0x000020EB, &axi_qos->qosctset0);
+       writel(0x00002096, &axi_qos->qosctset1);
+       writel(0x00002030, &axi_qos->qosctset2);
+       writel(0x00002030, &axi_qos->qosctset3);
+       writel(0x00000001, &axi_qos->qosreqctr);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00000000, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)SYS_AXI256_MXI_BASE;
+       writel(0x00000002, &axi_qos->qosconf);
+       writel(0x000020EB, &axi_qos->qosctset0);
+       writel(0x00002096, &axi_qos->qosctset1);
+       writel(0x00002030, &axi_qos->qosctset2);
+       writel(0x00002030, &axi_qos->qosctset3);
+       writel(0x00000001, &axi_qos->qosreqctr);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00000000, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       /* QoS Register (CCI-AXI) */
+       axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUS0_BASE;
+       writel(0x00000001, &axi_qos->qosconf);
+       writel(0x00002004, &axi_qos->qosctset0);
+       writel(0x00002096, &axi_qos->qosctset1);
+       writel(0x00002030, &axi_qos->qosctset2);
+       writel(0x00002030, &axi_qos->qosctset3);
+       writel(0x00000001, &axi_qos->qosreqctr);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00000000, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)CCI_AXI_SYX2_BASE;
+       writel(0x00000002, &axi_qos->qosconf);
+       writel(0x00002245, &axi_qos->qosctset0);
+       writel(0x00002096, &axi_qos->qosctset1);
+       writel(0x00002030, &axi_qos->qosctset2);
+       writel(0x00002030, &axi_qos->qosctset3);
+       writel(0x00000001, &axi_qos->qosreqctr);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00000000, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUR_BASE;
+       writel(0x00000001, &axi_qos->qosconf);
+       writel(0x00002004, &axi_qos->qosctset0);
+       writel(0x00002096, &axi_qos->qosctset1);
+       writel(0x00002030, &axi_qos->qosctset2);
+       writel(0x00002030, &axi_qos->qosctset3);
+       writel(0x00000001, &axi_qos->qosreqctr);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00000000, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUDS_BASE;
+       writel(0x00000001, &axi_qos->qosconf);
+       writel(0x00002004, &axi_qos->qosctset0);
+       writel(0x00002096, &axi_qos->qosctset1);
+       writel(0x00002030, &axi_qos->qosctset2);
+       writel(0x00002030, &axi_qos->qosctset3);
+       writel(0x00000001, &axi_qos->qosreqctr);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00000000, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUM_BASE;
+       writel(0x00000001, &axi_qos->qosconf);
+       writel(0x00002004, &axi_qos->qosctset0);
+       writel(0x00002096, &axi_qos->qosctset1);
+       writel(0x00002030, &axi_qos->qosctset2);
+       writel(0x00002030, &axi_qos->qosctset3);
+       writel(0x00000001, &axi_qos->qosreqctr);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00000000, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)CCI_AXI_MXI_BASE;
+       writel(0x00000002, &axi_qos->qosconf);
+       writel(0x00002245, &axi_qos->qosctset0);
+       writel(0x00002096, &axi_qos->qosctset1);
+       writel(0x00002030, &axi_qos->qosctset2);
+       writel(0x00002030, &axi_qos->qosctset3);
+       writel(0x00000001, &axi_qos->qosreqctr);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00000000, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUS1_BASE;
+       writel(0x00000001, &axi_qos->qosconf);
+       writel(0x00002004, &axi_qos->qosctset0);
+       writel(0x00002096, &axi_qos->qosctset1);
+       writel(0x00002030, &axi_qos->qosctset2);
+       writel(0x00002030, &axi_qos->qosctset3);
+       writel(0x00000001, &axi_qos->qosreqctr);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00000000, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUMP_BASE;
+       writel(0x00000001, &axi_qos->qosconf);
+       writel(0x00002004, &axi_qos->qosctset0);
+       writel(0x00002096, &axi_qos->qosctset1);
+       writel(0x00002030, &axi_qos->qosctset2);
+       writel(0x00002030, &axi_qos->qosctset3);
+       writel(0x00000001, &axi_qos->qosreqctr);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00000000, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       /* QoS Register (Media-AXI) */
+       axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_MXR_BASE;
+       writel(0x00000002, &axi_qos->qosconf);
+       writel(0x000020DC, &axi_qos->qosctset0);
+       writel(0x00002096, &axi_qos->qosctset1);
+       writel(0x00002030, &axi_qos->qosctset2);
+       writel(0x00002030, &axi_qos->qosctset3);
+       writel(0x00000020, &axi_qos->qosreqctr);
+       writel(0x000020AA, &axi_qos->qosthres0);
+       writel(0x00002032, &axi_qos->qosthres1);
+       writel(0x00000001, &axi_qos->qosthres2);
+
+       axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_MXW_BASE;
+       writel(0x00000002, &axi_qos->qosconf);
+       writel(0x000020DC, &axi_qos->qosctset0);
+       writel(0x00002096, &axi_qos->qosctset1);
+       writel(0x00002030, &axi_qos->qosctset2);
+       writel(0x00002030, &axi_qos->qosctset3);
+       writel(0x00000020, &axi_qos->qosreqctr);
+       writel(0x000020AA, &axi_qos->qosthres0);
+       writel(0x00002032, &axi_qos->qosthres1);
+       writel(0x00000001, &axi_qos->qosthres2);
+
+       axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_TDMR_BASE;
+       writel(0x00000001, &axi_qos->qosconf);
+       writel(0x00002190, &axi_qos->qosctset0);
+       writel(0x00000020, &axi_qos->qosreqctr);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00000001, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_TDMW_BASE;
+       writel(0x00000001, &axi_qos->qosconf);
+       writel(0x00002190, &axi_qos->qosctset0);
+       writel(0x00000020, &axi_qos->qosreqctr);
+       writel(0x00000001, &axi_qos->qosthres0);
+       writel(0x00000001, &axi_qos->qosthres1);
+       writel(0x00000001, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP1CR_BASE;
+       writel(0x00000001, &axi_qos->qosconf);
+       writel(0x00002190, &axi_qos->qosctset0);
+       writel(0x00000020, &axi_qos->qosreqctr);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00000001, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP1CW_BASE;
+       writel(0x00000001, &axi_qos->qosconf);
+       writel(0x00002190, &axi_qos->qosctset0);
+       writel(0x00000020, &axi_qos->qosreqctr);
+       writel(0x00000001, &axi_qos->qosthres0);
+       writel(0x00000001, &axi_qos->qosthres1);
+       writel(0x00000001, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPDU0CR_BASE;
+       writel(0x00000001, &axi_qos->qosconf);
+       writel(0x00002190, &axi_qos->qosctset0);
+       writel(0x00000020, &axi_qos->qosreqctr);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00000001, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPDU0CW_BASE;
+       writel(0x00000001, &axi_qos->qosconf);
+       writel(0x00002190, &axi_qos->qosctset0);
+       writel(0x00000020, &axi_qos->qosreqctr);
+       writel(0x00000001, &axi_qos->qosthres0);
+       writel(0x00000001, &axi_qos->qosthres1);
+       writel(0x00000001, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VIN0W_BASE;
+       writel(0x00000001, &axi_qos->qosconf);
+       writel(0x00001FF0, &axi_qos->qosctset0);
+       writel(0x00000020, &axi_qos->qosreqctr);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00002001, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_FDP0R_BASE;
+       writel(0x00000001, &axi_qos->qosconf);
+       writel(0x000020C8, &axi_qos->qosctset0);
+       writel(0x00000020, &axi_qos->qosreqctr);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00000001, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_FDP0W_BASE;
+       writel(0x00000001, &axi_qos->qosconf);
+       writel(0x000020C8, &axi_qos->qosctset0);
+       writel(0x00000020, &axi_qos->qosreqctr);
+       writel(0x00000001, &axi_qos->qosthres0);
+       writel(0x00000001, &axi_qos->qosthres1);
+       writel(0x00000001, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMSR_BASE;
+       writel(0x00000001, &axi_qos->qosconf);
+       writel(0x000020C8, &axi_qos->qosctset0);
+       writel(0x00000020, &axi_qos->qosreqctr);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00000001, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMSW_BASE;
+       writel(0x00000001, &axi_qos->qosconf);
+       writel(0x000020C8, &axi_qos->qosctset0);
+       writel(0x00000020, &axi_qos->qosreqctr);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00000001, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP1R_BASE;
+       writel(0x00000001, &axi_qos->qosconf);
+       writel(0x000020C8, &axi_qos->qosctset0);
+       writel(0x00000020, &axi_qos->qosreqctr);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00000001, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP1W_BASE;
+       writel(0x00000001, &axi_qos->qosconf);
+       writel(0x000020C8, &axi_qos->qosctset0);
+       writel(0x00000020, &axi_qos->qosreqctr);
+       writel(0x00000001, &axi_qos->qosthres0);
+       writel(0x00000001, &axi_qos->qosthres1);
+       writel(0x00000001, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMRR_BASE;
+       writel(0x00000001, &axi_qos->qosconf);
+       writel(0x000020C8, &axi_qos->qosctset0);
+       writel(0x00000020, &axi_qos->qosreqctr);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00000001, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMRW_BASE;
+       writel(0x00000001, &axi_qos->qosconf);
+       writel(0x000020C8, &axi_qos->qosctset0);
+       writel(0x00000020, &axi_qos->qosreqctr);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00000001, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPD0R_BASE;
+       writel(0x00000003, &axi_qos->qosconf);
+       writel(0x000020C8, &axi_qos->qosctset0);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00000001, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPD0W_BASE;
+       writel(0x00000003, &axi_qos->qosconf);
+       writel(0x000020C8, &axi_qos->qosctset0);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00000001, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_DU0R_BASE;
+       writel(0x00000003, &axi_qos->qosconf);
+       writel(0x00002063, &axi_qos->qosctset0);
+       writel(0x00000001, &axi_qos->qosreqctr);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00000001, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_DU0W_BASE;
+       writel(0x00000003, &axi_qos->qosconf);
+       writel(0x00002063, &axi_qos->qosctset0);
+       writel(0x00000001, &axi_qos->qosreqctr);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00000001, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP0CR_BASE;
+       writel(0x00000001, &axi_qos->qosconf);
+       writel(0x00002073, &axi_qos->qosctset0);
+       writel(0x00000020, &axi_qos->qosreqctr);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00000001, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP0CW_BASE;
+       writel(0x00000001, &axi_qos->qosconf);
+       writel(0x00002073, &axi_qos->qosctset0);
+       writel(0x00000020, &axi_qos->qosreqctr);
+       writel(0x00000001, &axi_qos->qosthres0);
+       writel(0x00000001, &axi_qos->qosthres1);
+       writel(0x00000001, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP0VR_BASE;
+       writel(0x00000001, &axi_qos->qosconf);
+       writel(0x00002073, &axi_qos->qosctset0);
+       writel(0x00000020, &axi_qos->qosreqctr);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00000001, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP0VW_BASE;
+       writel(0x00000001, &axi_qos->qosconf);
+       writel(0x00002073, &axi_qos->qosctset0);
+       writel(0x00000020, &axi_qos->qosreqctr);
+       writel(0x00000001, &axi_qos->qosthres0);
+       writel(0x00000001, &axi_qos->qosthres1);
+       writel(0x00000001, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VPC0R_BASE;
+       writel(0x00000001, &axi_qos->qosconf);
+       writel(0x00002073, &axi_qos->qosctset0);
+       writel(0x00000020, &axi_qos->qosreqctr);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00000001, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+}
+#else /* CONFIG_RMOBILE_EXTRAM_BOOT */
+void qos_init(void)
+{
+}
+#endif /* CONFIG_RMOBILE_EXTRAM_BOOT */

diff --git a/board/renesas/silk/qos.h b/board/renesas/silk/qos.h
new file mode 100644 (file)
index 0000000..75a20bb
--- /dev/null
+++ b/board/renesas/silk/qos.h
@@ -0,0 +1,13 @@
+/*
+ * Copyright (C) 2015 Renesas Electronics Corporation
+ * Copyright (C) 2015 Cogent Embedded, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#ifndef __QOS_H__
+#define __QOS_H__
+
+void qos_init(void);
+
+#endif

diff --git a/board/renesas/silk/silk.c b/board/renesas/silk/silk.c
new file mode 100644 (file)
index 0000000..dfd9a9d
--- /dev/null
+++ b/board/renesas/silk/silk.c
@@ -0,0 +1,163 @@
+/*
+ * board/renesas/silk/silk.c
+ *
+ * Copyright (C) 2015 Renesas Electronics Corporation
+ * Copyright (C) 2015 Cogent Embedded, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <asm/processor.h>
+#include <asm/mach-types.h>
+#include <asm/io.h>
+#include <asm/errno.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/gpio.h>
+#include <asm/arch/rmobile.h>
+#include <asm/arch/rcar-mstp.h>
+#include <asm/arch/mmc.h>
+#include <netdev.h>
+#include <miiphy.h>
+#include <i2c.h>
+#include <div64.h>
+#include "qos.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define CLK2MHZ(clk)   (clk / 1000 / 1000)
+void s_init(void)
+{
+       struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE;
+       struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE;
+
+       /* Watchdog init */
+       writel(0xA5A5A500, &rwdt->rwtcsra);
+       writel(0xA5A5A500, &swdt->swtcsra);
+
+       /* QoS */
+       qos_init();
+}
+
+#define TMU0_MSTP125   (1 << 25)
+#define SCIF2_MSTP719  (1 << 19)
+#define ETHER_MSTP813  (1 << 13)
+#define IIC1_MSTP323   (1 << 23)
+#define MMC0_MSTP315   (1 << 15)
+
+int board_early_init_f(void)
+{
+       /* TMU */
+       mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
+
+       /* SCIF2 */
+       mstp_clrbits_le32(MSTPSR7, SMSTPCR7, SCIF2_MSTP719);
+
+       /* ETHER */
+       mstp_clrbits_le32(MSTPSR8, SMSTPCR8, ETHER_MSTP813);
+
+       /* IIC1 / sh-i2c ch1 */
+       mstp_clrbits_le32(MSTPSR3, SMSTPCR3, IIC1_MSTP323);
+
+#ifdef CONFIG_SH_MMCIF
+       /* MMC */
+       mstp_clrbits_le32(MSTPSR3, SMSTPCR3, MMC0_MSTP315);
+#endif
+       return 0;
+}
+
+int board_init(void)
+{
+       /* adress of boot parameters */
+       gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+       /* Init PFC controller */
+       r8a7794_pinmux_init();
+
+       /* Ether Enable */
+       gpio_request(GPIO_FN_ETH_CRS_DV, NULL);
+       gpio_request(GPIO_FN_ETH_RX_ER, NULL);
+       gpio_request(GPIO_FN_ETH_RXD0, NULL);
+       gpio_request(GPIO_FN_ETH_RXD1, NULL);
+       gpio_request(GPIO_FN_ETH_LINK, NULL);
+       gpio_request(GPIO_FN_ETH_REFCLK, NULL);
+       gpio_request(GPIO_FN_ETH_MDIO, NULL);
+       gpio_request(GPIO_FN_ETH_TXD1, NULL);
+       gpio_request(GPIO_FN_ETH_TX_EN, NULL);
+       gpio_request(GPIO_FN_ETH_MAGIC, NULL);
+       gpio_request(GPIO_FN_ETH_TXD0, NULL);
+       gpio_request(GPIO_FN_ETH_MDC, NULL);
+       gpio_request(GPIO_FN_IRQ8, NULL);
+
+       /* PHY reset */
+       gpio_request(GPIO_GP_1_24, NULL);
+       gpio_direction_output(GPIO_GP_1_24, 0);
+       mdelay(20);
+       gpio_set_value(GPIO_GP_1_24, 1);
+       udelay(1);
+
+       return 0;
+}
+
+#define CXR24 0xEE7003C0 /* MAC address high register */
+#define CXR25 0xEE7003C8 /* MAC address low register */
+int board_eth_init(bd_t *bis)
+{
+#ifdef CONFIG_SH_ETHER
+       int ret = -ENODEV;
+       u32 val;
+       unsigned char enetaddr[6];
+
+       ret = sh_eth_initialize(bis);
+       if (!eth_getenv_enetaddr("ethaddr", enetaddr))
+               return ret;
+
+       /* Set Mac address */
+       val = enetaddr[0] << 24 | enetaddr[1] << 16 |
+               enetaddr[2] << 8 | enetaddr[3];
+       writel(val, CXR24);
+
+       val = enetaddr[4] << 8 | enetaddr[5];
+       writel(val, CXR25);
+
+       return ret;
+#else
+       return 0;
+#endif
+}
+
+int board_mmc_init(bd_t *bis)
+{
+       int ret = 0;
+
+#ifdef CONFIG_SH_MMCIF
+       /* MMC0 */
+       gpio_request(GPIO_GP_4_31, NULL);
+       gpio_set_value(GPIO_GP_4_31, 1);
+
+       ret = mmcif_mmc_init();
+#endif
+       return ret;
+}
+
+int dram_init(void)
+{
+       gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
+
+       return 0;
+}
+
+const struct rmobile_sysinfo sysinfo = {
+       CONFIG_RMOBILE_BOARD_STRING
+};
+
+void reset_cpu(ulong addr)
+{
+       u8 val;
+
+       i2c_set_bus_num(1); /* PowerIC connected to ch1 */
+       i2c_read(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1);
+       val |= 0x02;
+       i2c_write(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1);
+}

diff --git a/configs/axs103_defconfig b/configs/axs103_defconfig
new file mode 100644 (file)
index 0000000..c63dd4a
--- /dev/null
+++ b/configs/axs103_defconfig
@@ -0,0 +1,5 @@
+CONFIG_SYS_TEXT_BASE=0x81000000
+CONFIG_SYS_CLK_FREQ=50000000
+CONFIG_ARC=y
+CONFIG_ISA_ARCV2=y
+CONFIG_TARGET_AXS101=y

diff --git a/configs/silk_defconfig b/configs/silk_defconfig
new file mode 100644 (file)
index 0000000..515ee33
--- /dev/null
+++ b/configs/silk_defconfig
@@ -0,0 +1,3 @@
+CONFIG_ARM=y
+CONFIG_RMOBILE=y
+CONFIG_TARGET_SILK=y

diff --git a/include/configs/silk.h b/include/configs/silk.h
new file mode 100644 (file)
index 0000000..a4235e9
--- /dev/null
+++ b/include/configs/silk.h
@@ -0,0 +1,117 @@
+/*
+ * include/configs/silk.h
+ *     This file is silk board configuration.
+ *
+ * Copyright (C) 2015 Renesas Electronics Corporation
+ * Copyright (C) 2015 Cogent Embedded, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#ifndef __SILK_H
+#define __SILK_H
+
+#undef DEBUG
+#define CONFIG_R8A7794
+#define CONFIG_RMOBILE_BOARD_STRING "Silk"
+
+#include "rcar-gen2-common.h"
+
+#if defined(CONFIG_RMOBILE_EXTRAM_BOOT)
+#define CONFIG_SYS_TEXT_BASE   0x70000000
+#else
+#define CONFIG_SYS_TEXT_BASE   0xE6304000
+#endif
+
+#if defined(CONFIG_RMOBILE_EXTRAM_BOOT)
+#define CONFIG_SYS_INIT_SP_ADDR                0x7003FFFC
+#else
+#define CONFIG_SYS_INIT_SP_ADDR                0xE633FFFC
+#endif
+#define STACK_AREA_SIZE                        0xC000
+#define LOW_LEVEL_MERAM_STACK \
+               (CONFIG_SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4)
+
+/* MEMORY */
+#define RCAR_GEN2_SDRAM_BASE           0x40000000
+#define RCAR_GEN2_SDRAM_SIZE           (1024u * 1024 * 1024)
+#define RCAR_GEN2_UBOOT_SDRAM_SIZE     (512 * 1024 * 1024)
+
+/* SCIF */
+#define CONFIG_SCIF_CONSOLE
+#define CONFIG_CONS_SCIF2
+#define CONFIG_SCIF_USE_EXT_CLK
+
+/* FLASH */
+#define CONFIG_SPI
+#define CONFIG_SPI_FLASH_BAR
+#define CONFIG_SH_QSPI
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_SPANSION
+#define CONFIG_SPI_FLASH_QUAD
+#define CONFIG_SYS_NO_FLASH
+
+/* SH Ether */
+#define        CONFIG_NET_MULTI
+#define CONFIG_SH_ETHER
+#define CONFIG_SH_ETHER_USE_PORT       0
+#define CONFIG_SH_ETHER_PHY_ADDR       0x1
+#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII
+#define CONFIG_SH_ETHER_CACHE_WRITEBACK
+#define CONFIG_SH_ETHER_CACHE_INVALIDATE
+#define CONFIG_SH_ETHER_ALIGNE_SIZE    64
+#define CONFIG_PHYLIB
+#define CONFIG_PHY_MICREL
+#define CONFIG_BITBANGMII
+#define CONFIG_BITBANGMII_MULTI
+
+/* Board Clock */
+#define RMOBILE_XTAL_CLK       20000000u
+#define CONFIG_SYS_CLK_FREQ    RMOBILE_XTAL_CLK
+#define CONFIG_SH_TMU_CLK_FREQ (CONFIG_SYS_CLK_FREQ / 2) /* EXT / 2 */
+#define CONFIG_PLL1_CLK_FREQ   (CONFIG_SYS_CLK_FREQ * 156 / 2)
+#define CONFIG_P_CLK_FREQ      (CONFIG_PLL1_CLK_FREQ / 24)
+#define CONFIG_SH_SCIF_CLK_FREQ        14745600 /* External Clock */
+
+#define CONFIG_SYS_TMU_CLK_DIV  4
+
+/* i2c */
+#define CONFIG_CMD_I2C
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_SH
+#define CONFIG_SYS_I2C_SLAVE           0x7F
+#define CONFIG_SYS_I2C_SH_NUM_CONTROLLERS      3
+#define CONFIG_SYS_I2C_SH_SPEED0       400000
+#define CONFIG_SYS_I2C_SH_SPEED1       400000
+#define CONFIG_SYS_I2C_SH_SPEED2       400000
+#define CONFIG_SH_I2C_DATA_HIGH                4
+#define CONFIG_SH_I2C_DATA_LOW         5
+#define CONFIG_SH_I2C_CLOCK            10000000
+
+#define CONFIG_SYS_I2C_POWERIC_ADDR    0x58 /* da9063 */
+
+/* USB */
+#define CONFIG_USB_STORAGE
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_RMOBILE
+#define CONFIG_USB_MAX_CONTROLLER_COUNT        2
+
+/* MMCIF */
+#define CONFIG_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_CMD_MMC
+#define CONFIG_SH_MMCIF
+#define CONFIG_SH_MMCIF_ADDR   0xee200000
+#define CONFIG_SH_MMCIF_CLK    48000000
+
+/* Module stop status bits */
+/* INTC-RT */
+#define CONFIG_SMSTP0_ENA      0x00400000
+/* MSIF */
+#define CONFIG_SMSTP2_ENA      0x00002000
+/* INTC-SYS, IRQC */
+#define CONFIG_SMSTP4_ENA      0x00000180
+/* SCIF2 */
+#define CONFIG_SMSTP7_ENA      0x00080000
+
+#endif /* __SILK_H */