* Describes the physical PCM data formating and clocking. Add new formats
* to the end.
*/
-#define SND_SOC_DAIFMT_I2S 0 /* I2S mode */
-#define SND_SOC_DAIFMT_RIGHT_J 1 /* Right Justified mode */
-#define SND_SOC_DAIFMT_LEFT_J 2 /* Left Justified mode */
-#define SND_SOC_DAIFMT_DSP_A 3 /* L data MSB after FRM LRC */
-#define SND_SOC_DAIFMT_DSP_B 4 /* L data MSB during FRM LRC */
-#define SND_SOC_DAIFMT_AC97 5 /* AC97 */
-#define SND_SOC_DAIFMT_PDM 6 /* Pulse density modulation */
+#define SND_SOC_DAIFMT_I2S 1 /* I2S mode */
+#define SND_SOC_DAIFMT_RIGHT_J 2 /* Right Justified mode */
+#define SND_SOC_DAIFMT_LEFT_J 3 /* Left Justified mode */
+#define SND_SOC_DAIFMT_DSP_A 4 /* L data MSB after FRM LRC */
+#define SND_SOC_DAIFMT_DSP_B 5 /* L data MSB during FRM LRC */
+#define SND_SOC_DAIFMT_AC97 6 /* AC97 */
+#define SND_SOC_DAIFMT_PDM 7 /* Pulse density modulation */
/* left and right justified also known as MSB and LSB respectively */
#define SND_SOC_DAIFMT_MSB SND_SOC_DAIFMT_LEFT_J
* DAI bit clocks can be be gated (disabled) when the DAI is not
* sending or receiving PCM data in a frame. This can be used to save power.
*/
-#define SND_SOC_DAIFMT_CONT (0 << 4) /* continuous clock */
-#define SND_SOC_DAIFMT_GATED (1 << 4) /* clock is gated */
+#define SND_SOC_DAIFMT_CONT (1 << 4) /* continuous clock */
+#define SND_SOC_DAIFMT_GATED (2 << 4) /* clock is gated */
/*
* DAI hardware signal inversions.
* Specifies whether the DAI can also support inverted clocks for the specified
* format.
*/
-#define SND_SOC_DAIFMT_NB_NF (0 << 8) /* normal bit clock + frame */
-#define SND_SOC_DAIFMT_NB_IF (1 << 8) /* normal BCLK + inv FRM */
-#define SND_SOC_DAIFMT_IB_NF (2 << 8) /* invert BCLK + nor FRM */
-#define SND_SOC_DAIFMT_IB_IF (3 << 8) /* invert BCLK + FRM */
+#define SND_SOC_DAIFMT_NB_NF (1 << 8) /* normal bit clock + frame */
+#define SND_SOC_DAIFMT_NB_IF (2 << 8) /* normal BCLK + inv FRM */
+#define SND_SOC_DAIFMT_IB_NF (3 << 8) /* invert BCLK + nor FRM */
+#define SND_SOC_DAIFMT_IB_IF (4 << 8) /* invert BCLK + FRM */
/*
* DAI hardware clock masters.
* i.e. if the codec is clk and FRM master then the interface is
* clk and frame slave.
*/
-#define SND_SOC_DAIFMT_CBM_CFM (0 << 12) /* codec clk & FRM master */
-#define SND_SOC_DAIFMT_CBS_CFM (1 << 12) /* codec clk slave & FRM master */
-#define SND_SOC_DAIFMT_CBM_CFS (2 << 12) /* codec clk master & frame slave */
-#define SND_SOC_DAIFMT_CBS_CFS (3 << 12) /* codec clk & FRM slave */
+#define SND_SOC_DAIFMT_CBM_CFM (1 << 12) /* codec clk & FRM master */
+#define SND_SOC_DAIFMT_CBS_CFM (2 << 12) /* codec clk slave & FRM master */
+#define SND_SOC_DAIFMT_CBM_CFS (3 << 12) /* codec clk master & frame slave */
+#define SND_SOC_DAIFMT_CBS_CFS (4 << 12) /* codec clk & FRM slave */
#define SND_SOC_DAIFMT_FORMAT_MASK 0x000f
#define SND_SOC_DAIFMT_CLOCK_MASK 0x00f0
struct snd_soc_codec *codec;
struct snd_soc_codec_conf *codec_conf;
enum snd_soc_compress_type compress_type;
+ struct snd_soc_dai_link *dai_link;
int ret, i, order;
mutex_lock(&card->mutex);
snd_soc_dapm_add_routes(&card->dapm, card->dapm_routes,
card->num_dapm_routes);
+ for (i = 0; i < card->num_links; i++) {
+ dai_link = &card->dai_link[i];
+
+ if (dai_link->dai_fmt) {
+ ret = snd_soc_dai_set_fmt(card->rtd[i].codec_dai,
+ dai_link->dai_fmt);
+ if (ret != 0)
+ dev_warn(card->rtd[i].codec_dai->dev,
+ "Failed to set DAI format: %d\n",
+ ret);
+
+ ret = snd_soc_dai_set_fmt(card->rtd[i].cpu_dai,
+ dai_link->dai_fmt);
+ if (ret != 0)
+ dev_warn(card->rtd[i].cpu_dai->dev,
+ "Failed to set DAI format: %d\n",
+ ret);
+ }
+ }
+
snprintf(card->snd_card->shortname, sizeof(card->snd_card->shortname),
"%s", card->name);
snprintf(card->snd_card->longname, sizeof(card->snd_card->longname),