]> git.karo-electronics.de Git - linux-beck.git/commitdiff
ARM: dts: rockchip: add usb phys to Cortex-A9 socs
authorHeiko Stuebner <heiko@sntech.de>
Sat, 1 Aug 2015 18:28:36 +0000 (20:28 +0200)
committerHeiko Stuebner <heiko@sntech.de>
Sat, 8 Aug 2015 10:25:35 +0000 (12:25 +0200)
This adds the usbphy nodes to rk3066 and rk3188, which share the usb hosts
in rk3xxx.dtsi and also enables it on boards based around these socs.

The usb-phy itself is the same as used on the rk3288 already.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
arch/arm/boot/dts/rk3066a-marsboard.dts
arch/arm/boot/dts/rk3066a-rayeager.dts
arch/arm/boot/dts/rk3066a.dtsi
arch/arm/boot/dts/rk3188-radxarock.dts
arch/arm/boot/dts/rk3188.dtsi
arch/arm/boot/dts/rk3xxx.dtsi

index 4355966bb8daff98a56bbde5c0eecf819a8861dd..08f5b43171ebd4c4c8c4a5689f2f41ddb807ab0b 100644 (file)
        status = "okay";
 };
 
+&usbphy {
+       status = "okay";
+};
+
 &wdt {
        status = "okay";
 };
index 7ccd37671c2809c4ad9e7da21ee187291604e725..e36383c701dc5a9ecbd8ae67345e587264b75d9f 100644 (file)
        status = "okay";
 };
 
+&usbphy {
+       status = "okay";
+};
+
 &usb_otg {
        status = "okay";
 };
index d32229b8a996ec480504ce976181776e662dbd48..946f18705e965cb6fdfa357d0839bb594637f14a 100644 (file)
                clock-names = "timer", "pclk";
        };
 
+       usbphy: phy {
+               compatible = "rockchip,rk3066a-usb-phy", "rockchip,rk3288-usb-phy";
+               rockchip,grf = <&grf>;
+               #address-cells = <1>;
+               #size-cells = <0>;
+               status = "disabled";
+
+               usbphy0: usb-phy0 {
+                       #phy-cells = <0>;
+                       reg = <0x17c>;
+                       clocks = <&cru SCLK_OTGPHY0>;
+                       clock-names = "phyclk";
+               };
+
+               usbphy1: usb-phy1 {
+                       #phy-cells = <0>;
+                       reg = <0x188>;
+                       clocks = <&cru SCLK_OTGPHY1>;
+                       clock-names = "phyclk";
+               };
+       };
+
        pinctrl: pinctrl {
                compatible = "rockchip,rk3066a-pinctrl";
                rockchip,grf = <&grf>;
index 4bb014d4401a34128bf1ce839f4c97cdeb7aefbf..d2180e5d2b055c239cbf006f666ecc9358e69f8d 100644 (file)
        status = "okay";
 };
 
+&usbphy {
+       status = "okay";
+};
+
 &usb_host {
        status = "okay";
 };
index 0f23aedf9349d4c2fa3a36dca3691b3792a3a566..3163042721185af85c80a32a1fa5b18e69574189 100644 (file)
                #reset-cells = <1>;
        };
 
+       usbphy: phy {
+               compatible = "rockchip,rk3188-usb-phy", "rockchip,rk3288-usb-phy";
+               rockchip,grf = <&grf>;
+               #address-cells = <1>;
+               #size-cells = <0>;
+               status = "disabled";
+
+               usbphy0: usb-phy0 {
+                       #phy-cells = <0>;
+                       reg = <0x10c>;
+                       clocks = <&cru SCLK_OTGPHY0>;
+                       clock-names = "phyclk";
+               };
+
+               usbphy1: usb-phy1 {
+                       #phy-cells = <0>;
+                       reg = <0x11c>;
+                       clocks = <&cru SCLK_OTGPHY1>;
+                       clock-names = "phyclk";
+               };
+       };
+
        pinctrl: pinctrl {
                compatible = "rockchip,rk3188-pinctrl";
                rockchip,grf = <&grf>;
index c571ac87a4ff6ff6f177ccaf23c8e61fc6f0ce38..4497d288a7cbdb5e837279a1e67f0358da9582c5 100644 (file)
                g-rx-fifo-size = <275>;
                g-tx-fifo-size = <256 128 128 64 64 32>;
                g-use-dma;
+               phys = <&usbphy0>;
+               phy-names = "usb2-phy";
                status = "disabled";
        };
 
                clocks = <&cru HCLK_OTG1>;
                clock-names = "otg";
                dr_mode = "host";
+               phys = <&usbphy1>;
+               phy-names = "usb2-phy";
                status = "disabled";
        };