MIPS: BCM63XX: Handle SW IRQs 0-1

MIPS software IRQs 0 and 1 are used for interprocessor signaling (IPI)
on BMIPS SMP.  Make the board support code aware of them.

Signed-off-by: Kevin Cernekee <cernekee@gmail.com>
[jogo@openwrt.org: move sw irqs behind timer irq]
Signed-off-by: Jonas Gorski <jogo@openwrt.org>
Cc: linux-mips@linux-mips.org
Cc: John Crispin <blogic@openwrt.org>
Cc: Maxime Bizon <mbizon@freebox.fr>
Cc: Florian Fainelli <florian@openwrt.org>
Patchwork: https://patchwork.linux-mips.org/patch/5354/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

diff --git a/arch/mips/bcm63xx/irq.c b/arch/mips/bcm63xx/irq.c
index c0ab3887f42ef8b355eed9971f04188be0b966d8..d744606e19e90b8e4d8711dc85d682f1bfef7349 100644 (file)
--- a/arch/mips/bcm63xx/irq.c
+++ b/arch/mips/bcm63xx/irq.c
@@ -294,6 +294,10 @@ asmlinkage void plat_irq_dispatch(void)
 
                if (cause & CAUSEF_IP7)
                        do_IRQ(7);
+               if (cause & CAUSEF_IP0)
+                       do_IRQ(0);
+               if (cause & CAUSEF_IP1)
+                       do_IRQ(1);
                if (cause & CAUSEF_IP2)
                        dispatch_internal();
                if (!is_ext_irq_cascaded) {