.iobase = soc ## _IPU_CTRL_BASE_ADDR, \
.irq_err = soc ## _INT_IPU_ERR, \
.irq = soc ## _INT_IPU_SYN, \
+ .irq_start = MXC_IPU_IRQ_START, \
+ .iosize = size, \
+ .init = ipu_init, \
+ .pg = ipu_pg, \
+ }
+
+#define imx6_ipuv3_data_entry_single(soc, id, size, ipu_init, ipu_pg) \
+ { \
+ .iobase = soc ## _IPU ## id ## _ARB_BASE_ADDR, \
+ .irq_err = soc ## _INT_IPU ## id ## _ERR, \
+ .irq = soc ## _INT_IPU ## id ## _SYN, \
+ .irq_start = MXC_IPU_IRQ_START, \
.iosize = size, \
.init = ipu_init, \
.pg = ipu_pg, \
clk_enable(hsc_clk);
/* setup MIPI module to legacy mode */
- __raw_writel(0xF00, hsc_addr);
+ writel(0xF00, hsc_addr);
/* CSI mode: reserved; DI control mode: legacy (from Freescale BSP) */
- __raw_writel(__raw_readl(hsc_addr + 0x800) | 0x30ff,
+ writel(readl(hsc_addr + 0x800) | 0x30ff,
hsc_addr + 0x800);
clk_disable(hsc_clk);
return ret;
}
-int __init mx51_ipuv3_init(void)
+int __init mx51_ipuv3_init(int id)
{
int ret = 0;
u32 val;
void mx51_ipuv3_pg(int enable)
{
if (enable) {
- __raw_writel(MXC_PGCR_PCR, MX51_PGC_IPU_PGCR);
- __raw_writel(MXC_PGSR_PSR, MX51_PGC_IPU_PGSR);
+ writel(MXC_PGCR_PCR, MX51_PGC_IPU_PGCR);
+ writel(MXC_PGSR_PSR, MX51_PGC_IPU_PGSR);
} else {
- __raw_writel(0x0, MX51_PGC_IPU_PGCR);
- if (__raw_readl(MX51_PGC_IPU_PGSR) & MXC_PGSR_PSR)
+ writel(0x0, MX51_PGC_IPU_PGCR);
+ if (readl(MX51_PGC_IPU_PGSR) & MXC_PGSR_PSR)
printk(KERN_DEBUG "power gating successful\n");
- __raw_writel(MXC_PGSR_PSR, MX51_PGC_IPU_PGSR);
+ writel(MXC_PGSR_PSR, MX51_PGC_IPU_PGSR);
}
}
#endif
#ifdef CONFIG_SOC_IMX53
-int __init mx53_ipuv3_init(void)
+int __init mx53_ipuv3_init(int id)
{
int ret = 0;
u32 val;
void mx53_ipuv3_pg(int enable)
{
if (enable) {
- __raw_writel(MXC_PGCR_PCR, MX53_PGC_IPU_PGCR);
- __raw_writel(MXC_PGSR_PSR, MX53_PGC_IPU_PGSR);
+ writel(MXC_PGCR_PCR, MX53_PGC_IPU_PGCR);
+ writel(MXC_PGSR_PSR, MX53_PGC_IPU_PGSR);
} else {
- __raw_writel(0x0, MX53_PGC_IPU_PGCR);
- if (__raw_readl(MX53_PGC_IPU_PGSR) & MXC_PGSR_PSR)
+ writel(0x0, MX53_PGC_IPU_PGCR);
+ if (readl(MX53_PGC_IPU_PGSR) & MXC_PGSR_PSR)
printk(KERN_DEBUG "power gating successful\n");
- __raw_writel(MXC_PGSR_PSR, MX53_PGC_IPU_PGSR);
+ writel(MXC_PGSR_PSR, MX53_PGC_IPU_PGSR);
}
}
mx53_ipuv3_init, mx53_ipuv3_pg);
#endif
+#ifdef CONFIG_SOC_IMX6Q
+int __init mx6q_ipuv3_init(int id)
+{
+ int ret = 0;
+ u32 val;
+
+ /* hard reset the IPU */
+ val = readl(MX6_IO_ADDRESS(SRC_BASE_ADDR));
+ if (id == 0)
+ val |= 1 << 3;
+ else
+ val |= 1 << 12;
+ writel(val, MX6_IO_ADDRESS(SRC_BASE_ADDR));
+
+ return ret;
+}
+
+void mx6q_ipuv3_pg(int enable)
+{
+ /*TODO*/
+}
+
+const struct imx_ipuv3_data imx6q_ipuv3_data[] __initconst = {
+ imx6_ipuv3_data_entry_single(MX6Q, 1, SZ_4M,
+ mx6q_ipuv3_init, mx6q_ipuv3_pg),
+ imx6_ipuv3_data_entry_single(MX6Q, 2, SZ_4M,
+ mx6q_ipuv3_init, mx6q_ipuv3_pg),
+};
+#endif
+
struct platform_device *__init imx_add_ipuv3(
+ const int id,
const struct imx_ipuv3_data *data,
struct imx_ipuv3_platform_data *pdata)
{
pdata->init = data->init;
pdata->pg = data->pg;
- return imx_add_platform_device("imx-ipuv3", -1,
+ return imx_add_platform_device("imx-ipuv3", id,
res, ARRAY_SIZE(res), pdata, sizeof(*pdata));
}
+struct platform_device *__init imx_add_ipuv3_fb(
+ const int id,
+ const struct ipuv3_fb_platform_data *pdata)
+{
+ if (pdata->res_size > 0) {
+ struct resource res[] = {
+ {
+ .start = pdata->res_base,
+ .end = pdata->res_base + pdata->res_size - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ };
+
+ return imx_add_platform_device_dmamask("mxc_sdc_fb",
+ id, res, ARRAY_SIZE(res), pdata,
+ sizeof(*pdata), DMA_BIT_MASK(32));
+ } else
+ return imx_add_platform_device_dmamask("mxc_sdc_fb", id,
+ NULL, 0, pdata, sizeof(*pdata),
+ DMA_BIT_MASK(32));
+}
#define NON_MUX_I 0x3FF
#define NON_PAD_I 0x7FF
+#define MX6Q_HIGH_DRV (PAD_CTL_DSE_240ohm)
#define MX6Q_UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
+#define MX6Q_DISP_PAD_CLT MX6Q_HIGH_DRV
#define MX6Q_I2C_PAD_CTRL (PAD_CTL_SRE_FAST | PAD_CTL_ODE | \
PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_DSE_40ohm | \
PAD_CTL_PUS_100K_UP | PAD_CTL_HYS | PAD_CTL_SPEED_MED)
(_MX6Q_PAD_EIM_BCLK__TPSMP_HDATA_31 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX6Q_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK \
- (_MX6Q_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+ (_MX6Q_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
#define MX6Q_PAD_DI0_DISP_CLK__IPU2_DI0_DISP_CLK \
- (_MX6Q_PAD_DI0_DISP_CLK__IPU2_DI0_DISP_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+ (_MX6Q_PAD_DI0_DISP_CLK__IPU2_DI0_DISP_CLK | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
#define MX6Q_PAD_DI0_DISP_CLK__MIPI_CORE_DPHY_TEST_OUT_28 \
(_MX6Q_PAD_DI0_DISP_CLK__MIPI_CORE_DPHY_TEST_OUT_28 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX6Q_PAD_DI0_DISP_CLK__SDMA_DEBUG_CORE_STATE_0 \
(_MX6Q_PAD_DI0_DISP_CLK__MMDC_MMDC_DEBUG_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX6Q_PAD_DI0_PIN15__IPU1_DI0_PIN15 \
- (_MX6Q_PAD_DI0_PIN15__IPU1_DI0_PIN15 | MUX_PAD_CTRL(NO_PAD_CTRL))
+ (_MX6Q_PAD_DI0_PIN15__IPU1_DI0_PIN15 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
#define MX6Q_PAD_DI0_PIN15__IPU2_DI0_PIN15 \
- (_MX6Q_PAD_DI0_PIN15__IPU2_DI0_PIN15 | MUX_PAD_CTRL(NO_PAD_CTRL))
+ (_MX6Q_PAD_DI0_PIN15__IPU2_DI0_PIN15 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
#define MX6Q_PAD_DI0_PIN15__AUDMUX_AUD6_TXC \
(_MX6Q_PAD_DI0_PIN15__AUDMUX_AUD6_TXC | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX6Q_PAD_DI0_PIN15__MIPI_CORE_DPHY_TEST_OUT_29 \
(_MX6Q_PAD_DI0_PIN15__MMDC_MMDC_DEBUG_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX6Q_PAD_DI0_PIN2__IPU1_DI0_PIN2 \
- (_MX6Q_PAD_DI0_PIN2__IPU1_DI0_PIN2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+ (_MX6Q_PAD_DI0_PIN2__IPU1_DI0_PIN2 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
#define MX6Q_PAD_DI0_PIN2__IPU2_DI0_PIN2 \
- (_MX6Q_PAD_DI0_PIN2__IPU2_DI0_PIN2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+ (_MX6Q_PAD_DI0_PIN2__IPU2_DI0_PIN2 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
#define MX6Q_PAD_DI0_PIN2__AUDMUX_AUD6_TXD \
(_MX6Q_PAD_DI0_PIN2__AUDMUX_AUD6_TXD | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX6Q_PAD_DI0_PIN2__MIPI_CORE_DPHY_TEST_OUT_30 \
(_MX6Q_PAD_DI0_PIN2__PL301_MX6QPER1_HADDR_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX6Q_PAD_DI0_PIN3__IPU1_DI0_PIN3 \
- (_MX6Q_PAD_DI0_PIN3__IPU1_DI0_PIN3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+ (_MX6Q_PAD_DI0_PIN3__IPU1_DI0_PIN3 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
#define MX6Q_PAD_DI0_PIN3__IPU2_DI0_PIN3 \
- (_MX6Q_PAD_DI0_PIN3__IPU2_DI0_PIN3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+ (_MX6Q_PAD_DI0_PIN3__IPU2_DI0_PIN3 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
#define MX6Q_PAD_DI0_PIN3__AUDMUX_AUD6_TXFS \
(_MX6Q_PAD_DI0_PIN3__AUDMUX_AUD6_TXFS | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX6Q_PAD_DI0_PIN3__MIPI_CORE_DPHY_TEST_OUT_31 \
(_MX6Q_PAD_DI0_PIN4__PL301_MX6QPER1_HADDR_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX6Q_PAD_DISP0_DAT0__IPU1_DISP0_DAT_0 \
- (_MX6Q_PAD_DISP0_DAT0__IPU1_DISP0_DAT_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+ (_MX6Q_PAD_DISP0_DAT0__IPU1_DISP0_DAT_0 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
#define MX6Q_PAD_DISP0_DAT0__IPU2_DISP0_DAT_0 \
- (_MX6Q_PAD_DISP0_DAT0__IPU2_DISP0_DAT_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+ (_MX6Q_PAD_DISP0_DAT0__IPU2_DISP0_DAT_0 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
#define MX6Q_PAD_DISP0_DAT0__ECSPI3_SCLK \
(_MX6Q_PAD_DISP0_DAT0__ECSPI3_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX6Q_PAD_DISP0_DAT0__USDHC1_USDHC_DEBUG_0 \
(_MX6Q_PAD_DISP0_DAT0__MMDC_MMDC_DEBUG_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX6Q_PAD_DISP0_DAT1__IPU1_DISP0_DAT_1 \
- (_MX6Q_PAD_DISP0_DAT1__IPU1_DISP0_DAT_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+ (_MX6Q_PAD_DISP0_DAT1__IPU1_DISP0_DAT_1 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
#define MX6Q_PAD_DISP0_DAT1__IPU2_DISP0_DAT_1 \
- (_MX6Q_PAD_DISP0_DAT1__IPU2_DISP0_DAT_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+ (_MX6Q_PAD_DISP0_DAT1__IPU2_DISP0_DAT_1 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
#define MX6Q_PAD_DISP0_DAT1__ECSPI3_MOSI \
(_MX6Q_PAD_DISP0_DAT1__ECSPI3_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX6Q_PAD_DISP0_DAT1__USDHC1_USDHC_DEBUG_1 \
(_MX6Q_PAD_DISP0_DAT1__PL301_MX6QPER1_HADDR_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX6Q_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2 \
- (_MX6Q_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+ (_MX6Q_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
#define MX6Q_PAD_DISP0_DAT2__IPU2_DISP0_DAT_2 \
- (_MX6Q_PAD_DISP0_DAT2__IPU2_DISP0_DAT_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+ (_MX6Q_PAD_DISP0_DAT2__IPU2_DISP0_DAT_2 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
#define MX6Q_PAD_DISP0_DAT2__ECSPI3_MISO \
(_MX6Q_PAD_DISP0_DAT2__ECSPI3_MISO | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX6Q_PAD_DISP0_DAT2__USDHC1_USDHC_DEBUG_2 \
(_MX6Q_PAD_DISP0_DAT2__PL301_MX6QPER1_HADDR_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX6Q_PAD_DISP0_DAT3__IPU1_DISP0_DAT_3 \
- (_MX6Q_PAD_DISP0_DAT3__IPU1_DISP0_DAT_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+ (_MX6Q_PAD_DISP0_DAT3__IPU1_DISP0_DAT_3 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
#define MX6Q_PAD_DISP0_DAT3__IPU2_DISP0_DAT_3 \
- (_MX6Q_PAD_DISP0_DAT3__IPU2_DISP0_DAT_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+ (_MX6Q_PAD_DISP0_DAT3__IPU2_DISP0_DAT_3 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
#define MX6Q_PAD_DISP0_DAT3__ECSPI3_SS0 \
(_MX6Q_PAD_DISP0_DAT3__ECSPI3_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX6Q_PAD_DISP0_DAT3__USDHC1_USDHC_DEBUG_3 \
(_MX6Q_PAD_DISP0_DAT3__PL301_MX6QPER1_HADDR_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX6Q_PAD_DISP0_DAT4__IPU1_DISP0_DAT_4 \
- (_MX6Q_PAD_DISP0_DAT4__IPU1_DISP0_DAT_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+ (_MX6Q_PAD_DISP0_DAT4__IPU1_DISP0_DAT_4 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
#define MX6Q_PAD_DISP0_DAT4__IPU2_DISP0_DAT_4 \
- (_MX6Q_PAD_DISP0_DAT4__IPU2_DISP0_DAT_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+ (_MX6Q_PAD_DISP0_DAT4__IPU2_DISP0_DAT_4 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
#define MX6Q_PAD_DISP0_DAT4__ECSPI3_SS1 \
(_MX6Q_PAD_DISP0_DAT4__ECSPI3_SS1 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX6Q_PAD_DISP0_DAT4__USDHC1_USDHC_DEBUG_4 \
(_MX6Q_PAD_DISP0_DAT4__PL301_MX6QPER1_HADDR_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX6Q_PAD_DISP0_DAT5__IPU1_DISP0_DAT_5 \
- (_MX6Q_PAD_DISP0_DAT5__IPU1_DISP0_DAT_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+ (_MX6Q_PAD_DISP0_DAT5__IPU1_DISP0_DAT_5 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
#define MX6Q_PAD_DISP0_DAT5__IPU2_DISP0_DAT_5 \
- (_MX6Q_PAD_DISP0_DAT5__IPU2_DISP0_DAT_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+ (_MX6Q_PAD_DISP0_DAT5__IPU2_DISP0_DAT_5 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
#define MX6Q_PAD_DISP0_DAT5__ECSPI3_SS2 \
(_MX6Q_PAD_DISP0_DAT5__ECSPI3_SS2 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX6Q_PAD_DISP0_DAT5__AUDMUX_AUD6_RXFS \
(_MX6Q_PAD_DISP0_DAT5__PL301_MX6QPER1_HADDR_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX6Q_PAD_DISP0_DAT6__IPU1_DISP0_DAT_6 \
- (_MX6Q_PAD_DISP0_DAT6__IPU1_DISP0_DAT_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+ (_MX6Q_PAD_DISP0_DAT6__IPU1_DISP0_DAT_6 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
#define MX6Q_PAD_DISP0_DAT6__IPU2_DISP0_DAT_6 \
- (_MX6Q_PAD_DISP0_DAT6__IPU2_DISP0_DAT_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+ (_MX6Q_PAD_DISP0_DAT6__IPU2_DISP0_DAT_6 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
#define MX6Q_PAD_DISP0_DAT6__ECSPI3_SS3 \
(_MX6Q_PAD_DISP0_DAT6__ECSPI3_SS3 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX6Q_PAD_DISP0_DAT6__AUDMUX_AUD6_RXC \
(_MX6Q_PAD_DISP0_DAT6__PL301_MX6QPER1_HADDR_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX6Q_PAD_DISP0_DAT7__IPU1_DISP0_DAT_7 \
- (_MX6Q_PAD_DISP0_DAT7__IPU1_DISP0_DAT_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+ (_MX6Q_PAD_DISP0_DAT7__IPU1_DISP0_DAT_7 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
#define MX6Q_PAD_DISP0_DAT7__IPU2_DISP0_DAT_7 \
- (_MX6Q_PAD_DISP0_DAT7__IPU2_DISP0_DAT_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+ (_MX6Q_PAD_DISP0_DAT7__IPU2_DISP0_DAT_7 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
#define MX6Q_PAD_DISP0_DAT7__ECSPI3_RDY \
(_MX6Q_PAD_DISP0_DAT7__ECSPI3_RDY | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX6Q_PAD_DISP0_DAT7__USDHC1_USDHC_DEBUG_5 \
(_MX6Q_PAD_DISP0_DAT7__PL301_MX6QPER1_HADDR_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX6Q_PAD_DISP0_DAT8__IPU1_DISP0_DAT_8 \
- (_MX6Q_PAD_DISP0_DAT8__IPU1_DISP0_DAT_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
+ (_MX6Q_PAD_DISP0_DAT8__IPU1_DISP0_DAT_8 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
#define MX6Q_PAD_DISP0_DAT8__IPU2_DISP0_DAT_8 \
- (_MX6Q_PAD_DISP0_DAT8__IPU2_DISP0_DAT_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
+ (_MX6Q_PAD_DISP0_DAT8__IPU2_DISP0_DAT_8 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
#define MX6Q_PAD_DISP0_DAT8__PWM1_PWMO \
(_MX6Q_PAD_DISP0_DAT8__PWM1_PWMO | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX6Q_PAD_DISP0_DAT8__WDOG1_WDOG_B \
(_MX6Q_PAD_DISP0_DAT8__PL301_MX6QPER1_HADDR_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX6Q_PAD_DISP0_DAT9__IPU1_DISP0_DAT_9 \
- (_MX6Q_PAD_DISP0_DAT9__IPU1_DISP0_DAT_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
+ (_MX6Q_PAD_DISP0_DAT9__IPU1_DISP0_DAT_9 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
#define MX6Q_PAD_DISP0_DAT9__IPU2_DISP0_DAT_9 \
- (_MX6Q_PAD_DISP0_DAT9__IPU2_DISP0_DAT_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
+ (_MX6Q_PAD_DISP0_DAT9__IPU2_DISP0_DAT_9 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
#define MX6Q_PAD_DISP0_DAT9__PWM2_PWMO \
(_MX6Q_PAD_DISP0_DAT9__PWM2_PWMO | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX6Q_PAD_DISP0_DAT9__WDOG2_WDOG_B \
(_MX6Q_PAD_DISP0_DAT9__PL301_MX6QPER1_HADDR_20 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX6Q_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10 \
- (_MX6Q_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
+ (_MX6Q_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
#define MX6Q_PAD_DISP0_DAT10__IPU2_DISP0_DAT_10 \
- (_MX6Q_PAD_DISP0_DAT10__IPU2_DISP0_DAT_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
+ (_MX6Q_PAD_DISP0_DAT10__IPU2_DISP0_DAT_10 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
#define MX6Q_PAD_DISP0_DAT10__USDHC1_USDHC_DEBUG_6 \
(_MX6Q_PAD_DISP0_DAT10__USDHC1_USDHC_DEBUG_6 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
#define MX6Q_PAD_DISP0_DAT10__SDMA_DEBUG_EVENT_CHANNEL_3 \
(_MX6Q_PAD_DISP0_DAT10__PL301_MX6QPER1_HADDR_21 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX6Q_PAD_DISP0_DAT11__IPU1_DISP0_DAT_11 \
- (_MX6Q_PAD_DISP0_DAT11__IPU1_DISP0_DAT_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
+ (_MX6Q_PAD_DISP0_DAT11__IPU1_DISP0_DAT_11 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
#define MX6Q_PAD_DISP0_DAT11__IPU2_DISP0_DAT_11 \
- (_MX6Q_PAD_DISP0_DAT11__IPU2_DISP0_DAT_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
+ (_MX6Q_PAD_DISP0_DAT11__IPU2_DISP0_DAT_11 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
#define MX6Q_PAD_DISP0_DAT11__USDHC1_USDHC_DEBUG_7 \
(_MX6Q_PAD_DISP0_DAT11__USDHC1_USDHC_DEBUG_7 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
#define MX6Q_PAD_DISP0_DAT11__SDMA_DEBUG_EVENT_CHANNEL_4 \
(_MX6Q_PAD_DISP0_DAT11__PL301_MX6QPER1_HADDR_22 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX6Q_PAD_DISP0_DAT12__IPU1_DISP0_DAT_12 \
- (_MX6Q_PAD_DISP0_DAT12__IPU1_DISP0_DAT_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
+ (_MX6Q_PAD_DISP0_DAT12__IPU1_DISP0_DAT_12 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
#define MX6Q_PAD_DISP0_DAT12__IPU2_DISP0_DAT_12 \
- (_MX6Q_PAD_DISP0_DAT12__IPU2_DISP0_DAT_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
+ (_MX6Q_PAD_DISP0_DAT12__IPU2_DISP0_DAT_12 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
#define MX6Q_PAD_DISP0_DAT12__RESERVED_RESERVED \
(_MX6Q_PAD_DISP0_DAT12__RESERVED_RESERVED | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX6Q_PAD_DISP0_DAT12__SDMA_DEBUG_EVENT_CHANNEL_5 \
(_MX6Q_PAD_DISP0_DAT12__PL301_MX6QPER1_HADDR_23 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX6Q_PAD_DISP0_DAT13__IPU1_DISP0_DAT_13 \
- (_MX6Q_PAD_DISP0_DAT13__IPU1_DISP0_DAT_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
+ (_MX6Q_PAD_DISP0_DAT13__IPU1_DISP0_DAT_13 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
#define MX6Q_PAD_DISP0_DAT13__IPU2_DISP0_DAT_13 \
- (_MX6Q_PAD_DISP0_DAT13__IPU2_DISP0_DAT_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
+ (_MX6Q_PAD_DISP0_DAT13__IPU2_DISP0_DAT_13 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
#define MX6Q_PAD_DISP0_DAT13__AUDMUX_AUD5_RXFS \
(_MX6Q_PAD_DISP0_DAT13__AUDMUX_AUD5_RXFS | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX6Q_PAD_DISP0_DAT13__SDMA_DEBUG_EVT_CHN_LINES_0 \
(_MX6Q_PAD_DISP0_DAT13__PL301_MX6QPER1_HADDR_24 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX6Q_PAD_DISP0_DAT14__IPU1_DISP0_DAT_14 \
- (_MX6Q_PAD_DISP0_DAT14__IPU1_DISP0_DAT_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
+ (_MX6Q_PAD_DISP0_DAT14__IPU1_DISP0_DAT_14 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
#define MX6Q_PAD_DISP0_DAT14__IPU2_DISP0_DAT_14 \
- (_MX6Q_PAD_DISP0_DAT14__IPU2_DISP0_DAT_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
+ (_MX6Q_PAD_DISP0_DAT14__IPU2_DISP0_DAT_14 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
#define MX6Q_PAD_DISP0_DAT14__AUDMUX_AUD5_RXC \
(_MX6Q_PAD_DISP0_DAT14__AUDMUX_AUD5_RXC | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX6Q_PAD_DISP0_DAT14__SDMA_DEBUG_EVT_CHN_LINES_1 \
(_MX6Q_PAD_DISP0_DAT14__MMDC_MMDC_DEBUG_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX6Q_PAD_DISP0_DAT15__IPU1_DISP0_DAT_15 \
- (_MX6Q_PAD_DISP0_DAT15__IPU1_DISP0_DAT_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
+ (_MX6Q_PAD_DISP0_DAT15__IPU1_DISP0_DAT_15 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
#define MX6Q_PAD_DISP0_DAT15__IPU2_DISP0_DAT_15 \
- (_MX6Q_PAD_DISP0_DAT15__IPU2_DISP0_DAT_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
+ (_MX6Q_PAD_DISP0_DAT15__IPU2_DISP0_DAT_15 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
#define MX6Q_PAD_DISP0_DAT15__ECSPI1_SS1 \
(_MX6Q_PAD_DISP0_DAT15__ECSPI1_SS1 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX6Q_PAD_DISP0_DAT15__ECSPI2_SS1 \
(_MX6Q_PAD_DISP0_DAT15__PL301_MX6QPER1_HADDR_25 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX6Q_PAD_DISP0_DAT16__IPU1_DISP0_DAT_16 \
- (_MX6Q_PAD_DISP0_DAT16__IPU1_DISP0_DAT_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
+ (_MX6Q_PAD_DISP0_DAT16__IPU1_DISP0_DAT_16 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
#define MX6Q_PAD_DISP0_DAT16__IPU2_DISP0_DAT_16 \
- (_MX6Q_PAD_DISP0_DAT16__IPU2_DISP0_DAT_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
+ (_MX6Q_PAD_DISP0_DAT16__IPU2_DISP0_DAT_16 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
#define MX6Q_PAD_DISP0_DAT16__ECSPI2_MOSI \
(_MX6Q_PAD_DISP0_DAT16__ECSPI2_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX6Q_PAD_DISP0_DAT16__AUDMUX_AUD5_TXC \
(_MX6Q_PAD_DISP0_DAT16__PL301_MX6QPER1_HADDR_26 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX6Q_PAD_DISP0_DAT17__IPU1_DISP0_DAT_17 \
- (_MX6Q_PAD_DISP0_DAT17__IPU1_DISP0_DAT_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
+ (_MX6Q_PAD_DISP0_DAT17__IPU1_DISP0_DAT_17 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
#define MX6Q_PAD_DISP0_DAT17__IPU2_DISP0_DAT_17 \
- (_MX6Q_PAD_DISP0_DAT17__IPU2_DISP0_DAT_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
+ (_MX6Q_PAD_DISP0_DAT17__IPU2_DISP0_DAT_17 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
#define MX6Q_PAD_DISP0_DAT17__ECSPI2_MISO \
(_MX6Q_PAD_DISP0_DAT17__ECSPI2_MISO | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX6Q_PAD_DISP0_DAT17__AUDMUX_AUD5_TXD \
(_MX6Q_PAD_DISP0_DAT17__PL301_MX6QPER1_HADDR_27 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX6Q_PAD_DISP0_DAT18__IPU1_DISP0_DAT_18 \
- (_MX6Q_PAD_DISP0_DAT18__IPU1_DISP0_DAT_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
+ (_MX6Q_PAD_DISP0_DAT18__IPU1_DISP0_DAT_18 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
#define MX6Q_PAD_DISP0_DAT18__IPU2_DISP0_DAT_18 \
- (_MX6Q_PAD_DISP0_DAT18__IPU2_DISP0_DAT_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
+ (_MX6Q_PAD_DISP0_DAT18__IPU2_DISP0_DAT_18 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
#define MX6Q_PAD_DISP0_DAT18__ECSPI2_SS0 \
(_MX6Q_PAD_DISP0_DAT18__ECSPI2_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX6Q_PAD_DISP0_DAT18__AUDMUX_AUD5_TXFS \
(_MX6Q_PAD_DISP0_DAT18__WEIM_WEIM_CS_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX6Q_PAD_DISP0_DAT19__IPU1_DISP0_DAT_19 \
- (_MX6Q_PAD_DISP0_DAT19__IPU1_DISP0_DAT_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
+ (_MX6Q_PAD_DISP0_DAT19__IPU1_DISP0_DAT_19 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
#define MX6Q_PAD_DISP0_DAT19__IPU2_DISP0_DAT_19 \
- (_MX6Q_PAD_DISP0_DAT19__IPU2_DISP0_DAT_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
+ (_MX6Q_PAD_DISP0_DAT19__IPU2_DISP0_DAT_19 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
#define MX6Q_PAD_DISP0_DAT19__ECSPI2_SCLK \
(_MX6Q_PAD_DISP0_DAT19__ECSPI2_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX6Q_PAD_DISP0_DAT19__AUDMUX_AUD5_RXD \
(_MX6Q_PAD_DISP0_DAT19__WEIM_WEIM_CS_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX6Q_PAD_DISP0_DAT20__IPU1_DISP0_DAT_20 \
- (_MX6Q_PAD_DISP0_DAT20__IPU1_DISP0_DAT_20 | MUX_PAD_CTRL(NO_PAD_CTRL))
+ (_MX6Q_PAD_DISP0_DAT20__IPU1_DISP0_DAT_20 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
#define MX6Q_PAD_DISP0_DAT20__IPU2_DISP0_DAT_20 \
- (_MX6Q_PAD_DISP0_DAT20__IPU2_DISP0_DAT_20 | MUX_PAD_CTRL(NO_PAD_CTRL))
+ (_MX6Q_PAD_DISP0_DAT20__IPU2_DISP0_DAT_20 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
#define MX6Q_PAD_DISP0_DAT20__ECSPI1_SCLK \
(_MX6Q_PAD_DISP0_DAT20__ECSPI1_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX6Q_PAD_DISP0_DAT20__AUDMUX_AUD4_TXC \
(_MX6Q_PAD_DISP0_DAT20__PL301_MX6QPER1_HADDR_28 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX6Q_PAD_DISP0_DAT21__IPU1_DISP0_DAT_21 \
- (_MX6Q_PAD_DISP0_DAT21__IPU1_DISP0_DAT_21 | MUX_PAD_CTRL(NO_PAD_CTRL))
+ (_MX6Q_PAD_DISP0_DAT21__IPU1_DISP0_DAT_21 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
#define MX6Q_PAD_DISP0_DAT21__IPU2_DISP0_DAT_21 \
- (_MX6Q_PAD_DISP0_DAT21__IPU2_DISP0_DAT_21 | MUX_PAD_CTRL(NO_PAD_CTRL))
+ (_MX6Q_PAD_DISP0_DAT21__IPU2_DISP0_DAT_21 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
#define MX6Q_PAD_DISP0_DAT21__ECSPI1_MOSI \
(_MX6Q_PAD_DISP0_DAT21__ECSPI1_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX6Q_PAD_DISP0_DAT21__AUDMUX_AUD4_TXD \
(_MX6Q_PAD_DISP0_DAT21__PL301_MX6QPER1_HADDR_29 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX6Q_PAD_DISP0_DAT22__IPU1_DISP0_DAT_22 \
- (_MX6Q_PAD_DISP0_DAT22__IPU1_DISP0_DAT_22 | MUX_PAD_CTRL(NO_PAD_CTRL))
+ (_MX6Q_PAD_DISP0_DAT22__IPU1_DISP0_DAT_22 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
#define MX6Q_PAD_DISP0_DAT22__IPU2_DISP0_DAT_22 \
- (_MX6Q_PAD_DISP0_DAT22__IPU2_DISP0_DAT_22 | MUX_PAD_CTRL(NO_PAD_CTRL))
+ (_MX6Q_PAD_DISP0_DAT22__IPU2_DISP0_DAT_22 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
#define MX6Q_PAD_DISP0_DAT22__ECSPI1_MISO \
(_MX6Q_PAD_DISP0_DAT22__ECSPI1_MISO | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX6Q_PAD_DISP0_DAT22__AUDMUX_AUD4_TXFS \
(_MX6Q_PAD_DISP0_DAT22__PL301_MX6QPER1_HADDR_30 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX6Q_PAD_DISP0_DAT23__IPU1_DISP0_DAT_23 \
- (_MX6Q_PAD_DISP0_DAT23__IPU1_DISP0_DAT_23 | MUX_PAD_CTRL(NO_PAD_CTRL))
+ (_MX6Q_PAD_DISP0_DAT23__IPU1_DISP0_DAT_23 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
#define MX6Q_PAD_DISP0_DAT23__IPU2_DISP0_DAT_23 \
- (_MX6Q_PAD_DISP0_DAT23__IPU2_DISP0_DAT_23 | MUX_PAD_CTRL(NO_PAD_CTRL))
+ (_MX6Q_PAD_DISP0_DAT23__IPU2_DISP0_DAT_23 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
#define MX6Q_PAD_DISP0_DAT23__ECSPI1_SS0 \
(_MX6Q_PAD_DISP0_DAT23__ECSPI1_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX6Q_PAD_DISP0_DAT23__AUDMUX_AUD4_RXD \
#define MX6Q_PAD_GPIO_9__PWM1_PWMO \
(_MX6Q_PAD_GPIO_9__PWM1_PWMO | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX6Q_PAD_GPIO_9__GPIO_1_9 \
- (_MX6Q_PAD_GPIO_9__GPIO_1_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
+ (_MX6Q_PAD_GPIO_9__GPIO_1_9 | MUX_PAD_CTRL(MX6Q_HIGH_DRV))
#define MX6Q_PAD_GPIO_9__USDHC1_WP \
(_MX6Q_PAD_GPIO_9__USDHC1_WP | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
#define MX6Q_PAD_GPIO_9__SRC_EARLY_RST \