drm/radeon: rework ring function handling

Give the ring functions a separate structure and let the asic
structure point to the ring specific functions. This simplifies
the code and allows us to make changes at only one point.

No change in functionality.

Signed-off-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
index 5e21dbeaf314b6133e710166dcaa1fad306be074..b26a20fe2859533f4b4b9949c4d4e41b8e8c65f4 100644 (file)
--- a/drivers/gpu/drm/radeon/radeon.h
+++ b/drivers/gpu/drm/radeon/radeon.h
@@ -1578,6 +1578,34 @@ int radeon_debugfs_add_files(struct radeon_device *rdev,
                             unsigned nfiles);
 int radeon_debugfs_fence_init(struct radeon_device *rdev);
 
+/*
+ * ASIC ring specific functions.
+ */
+struct radeon_asic_ring {
+       /* ring read/write ptr handling */
+       u32 (*get_rptr)(struct radeon_device *rdev, struct radeon_ring *ring);
+       u32 (*get_wptr)(struct radeon_device *rdev, struct radeon_ring *ring);
+       void (*set_wptr)(struct radeon_device *rdev, struct radeon_ring *ring);
+
+       /* validating and patching of IBs */
+       int (*ib_parse)(struct radeon_device *rdev, struct radeon_ib *ib);
+       int (*cs_parse)(struct radeon_cs_parser *p);
+
+       /* command emmit functions */
+       void (*ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib);
+       void (*emit_fence)(struct radeon_device *rdev, struct radeon_fence *fence);
+       void (*emit_semaphore)(struct radeon_device *rdev, struct radeon_ring *cp,
+                              struct radeon_semaphore *semaphore, bool emit_wait);
+       void (*vm_flush)(struct radeon_device *rdev, int ridx, struct radeon_vm *vm);
+
+       /* testing functions */
+       int (*ring_test)(struct radeon_device *rdev, struct radeon_ring *cp);
+       int (*ib_test)(struct radeon_device *rdev, struct radeon_ring *cp);
+       bool (*is_lockup)(struct radeon_device *rdev, struct radeon_ring *cp);
+
+       /* deprecated */
+       void (*ring_start)(struct radeon_device *rdev, struct radeon_ring *cp);
+};
 
 /*
  * ASIC specific functions.
@@ -1621,23 +1649,7 @@ struct radeon_asic {
                                 uint32_t incr, uint32_t flags);
        } vm;
        /* ring specific callbacks */
-       struct {
-               void (*ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib);
-               int (*ib_parse)(struct radeon_device *rdev, struct radeon_ib *ib);
-               void (*emit_fence)(struct radeon_device *rdev, struct radeon_fence *fence);
-               void (*emit_semaphore)(struct radeon_device *rdev, struct radeon_ring *cp,
-                                      struct radeon_semaphore *semaphore, bool emit_wait);
-               int (*cs_parse)(struct radeon_cs_parser *p);
-               void (*ring_start)(struct radeon_device *rdev, struct radeon_ring *cp);
-               int (*ring_test)(struct radeon_device *rdev, struct radeon_ring *cp);
-               int (*ib_test)(struct radeon_device *rdev, struct radeon_ring *cp);
-               bool (*is_lockup)(struct radeon_device *rdev, struct radeon_ring *cp);
-               void (*vm_flush)(struct radeon_device *rdev, int ridx, struct radeon_vm *vm);
-
-               u32 (*get_rptr)(struct radeon_device *rdev, struct radeon_ring *ring);
-               u32 (*get_wptr)(struct radeon_device *rdev, struct radeon_ring *ring);
-               void (*set_wptr)(struct radeon_device *rdev, struct radeon_ring *ring);
-       } ring[RADEON_NUM_RINGS];
+       struct radeon_asic_ring *ring[RADEON_NUM_RINGS];
        /* irqs */
        struct {
                int (*set)(struct radeon_device *rdev);
@@ -2442,7 +2454,7 @@ void radeon_ring_write(struct radeon_ring *ring, uint32_t v);
 #define radeon_fini(rdev) (rdev)->asic->fini((rdev))
 #define radeon_resume(rdev) (rdev)->asic->resume((rdev))
 #define radeon_suspend(rdev) (rdev)->asic->suspend((rdev))
-#define radeon_cs_parse(rdev, r, p) (rdev)->asic->ring[(r)].cs_parse((p))
+#define radeon_cs_parse(rdev, r, p) (rdev)->asic->ring[(r)]->cs_parse((p))
 #define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state))
 #define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev))
 #define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart.tlb_flush((rdev))
@@ -2450,16 +2462,16 @@ void radeon_ring_write(struct radeon_ring *ring, uint32_t v);
 #define radeon_asic_vm_init(rdev) (rdev)->asic->vm.init((rdev))
 #define radeon_asic_vm_fini(rdev) (rdev)->asic->vm.fini((rdev))
 #define radeon_asic_vm_set_page(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.set_page((rdev), (ib), (pe), (addr), (count), (incr), (flags)))
-#define radeon_ring_start(rdev, r, cp) (rdev)->asic->ring[(r)].ring_start((rdev), (cp))
-#define radeon_ring_test(rdev, r, cp) (rdev)->asic->ring[(r)].ring_test((rdev), (cp))
-#define radeon_ib_test(rdev, r, cp) (rdev)->asic->ring[(r)].ib_test((rdev), (cp))
-#define radeon_ring_ib_execute(rdev, r, ib) (rdev)->asic->ring[(r)].ib_execute((rdev), (ib))
-#define radeon_ring_ib_parse(rdev, r, ib) (rdev)->asic->ring[(r)].ib_parse((rdev), (ib))
-#define radeon_ring_is_lockup(rdev, r, cp) (rdev)->asic->ring[(r)].is_lockup((rdev), (cp))
-#define radeon_ring_vm_flush(rdev, r, vm) (rdev)->asic->ring[(r)].vm_flush((rdev), (r), (vm))
-#define radeon_ring_get_rptr(rdev, r) (rdev)->asic->ring[(r)->idx].get_rptr((rdev), (r))
-#define radeon_ring_get_wptr(rdev, r) (rdev)->asic->ring[(r)->idx].get_wptr((rdev), (r))
-#define radeon_ring_set_wptr(rdev, r) (rdev)->asic->ring[(r)->idx].set_wptr((rdev), (r))
+#define radeon_ring_start(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_start((rdev), (cp))
+#define radeon_ring_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_test((rdev), (cp))
+#define radeon_ib_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ib_test((rdev), (cp))
+#define radeon_ring_ib_execute(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_execute((rdev), (ib))
+#define radeon_ring_ib_parse(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_parse((rdev), (ib))
+#define radeon_ring_is_lockup(rdev, r, cp) (rdev)->asic->ring[(r)]->is_lockup((rdev), (cp))
+#define radeon_ring_vm_flush(rdev, r, vm) (rdev)->asic->ring[(r)]->vm_flush((rdev), (r), (vm))
+#define radeon_ring_get_rptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_rptr((rdev), (r))
+#define radeon_ring_get_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_wptr((rdev), (r))
+#define radeon_ring_set_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->set_wptr((rdev), (r))
 #define radeon_irq_set(rdev) (rdev)->asic->irq.set((rdev))
 #define radeon_irq_process(rdev) (rdev)->asic->irq.process((rdev))
 #define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->display.get_vblank_counter((rdev), (crtc))
@@ -2467,8 +2479,8 @@ void radeon_ring_write(struct radeon_ring *ring, uint32_t v);
 #define radeon_get_backlight_level(rdev, e) (rdev)->asic->display.get_backlight_level((e))
 #define radeon_hdmi_enable(rdev, e, b) (rdev)->asic->display.hdmi_enable((e), (b))
 #define radeon_hdmi_setmode(rdev, e, m) (rdev)->asic->display.hdmi_setmode((e), (m))
-#define radeon_fence_ring_emit(rdev, r, fence) (rdev)->asic->ring[(r)].emit_fence((rdev), (fence))
-#define radeon_semaphore_ring_emit(rdev, r, cp, semaphore, emit_wait) (rdev)->asic->ring[(r)].emit_semaphore((rdev), (cp), (semaphore), (emit_wait))
+#define radeon_fence_ring_emit(rdev, r, fence) (rdev)->asic->ring[(r)]->emit_fence((rdev), (fence))
+#define radeon_semaphore_ring_emit(rdev, r, cp, semaphore, emit_wait) (rdev)->asic->ring[(r)]->emit_semaphore((rdev), (cp), (semaphore), (emit_wait))
 #define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy.blit((rdev), (s), (d), (np), (f))
 #define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy.dma((rdev), (s), (d), (np), (f))
 #define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy.copy((rdev), (s), (d), (np), (f))

diff --git a/drivers/gpu/drm/radeon/radeon_asic.c b/drivers/gpu/drm/radeon/radeon_asic.c
index 61c06449b31a48e29600b88815e8e8b3b34e57a4..012fe7218c741c2e3f00f1102134b60ba9733a47 100644 (file)
--- a/drivers/gpu/drm/radeon/radeon_asic.c
+++ b/drivers/gpu/drm/radeon/radeon_asic.c
@@ -172,6 +172,21 @@ void radeon_agp_disable(struct radeon_device *rdev)
 /*
  * ASIC
  */
+
+static struct radeon_asic_ring r100_gfx_ring = {
+       .ib_execute = &r100_ring_ib_execute,
+       .emit_fence = &r100_fence_ring_emit,
+       .emit_semaphore = &r100_semaphore_ring_emit,
+       .cs_parse = &r100_cs_parse,
+       .ring_start = &r100_ring_start,
+       .ring_test = &r100_ring_test,
+       .ib_test = &r100_ib_test,
+       .is_lockup = &r100_gpu_is_lockup,
+       .get_rptr = &radeon_ring_generic_get_rptr,
+       .get_wptr = &radeon_ring_generic_get_wptr,
+       .set_wptr = &radeon_ring_generic_set_wptr,
+};
+
 static struct radeon_asic r100_asic = {
        .init = &r100_init,
        .fini = &r100_fini,
@@ -187,19 +202,7 @@ static struct radeon_asic r100_asic = {
                .set_page = &r100_pci_gart_set_page,
        },
        .ring = {
-               [RADEON_RING_TYPE_GFX_INDEX] = {
-                       .ib_execute = &r100_ring_ib_execute,
-                       .emit_fence = &r100_fence_ring_emit,
-                       .emit_semaphore = &r100_semaphore_ring_emit,
-                       .cs_parse = &r100_cs_parse,
-                       .ring_start = &r100_ring_start,
-                       .ring_test = &r100_ring_test,
-                       .ib_test = &r100_ib_test,
-                       .is_lockup = &r100_gpu_is_lockup,
-                       .get_rptr = &radeon_ring_generic_get_rptr,
-                       .get_wptr = &radeon_ring_generic_get_wptr,
-                       .set_wptr = &radeon_ring_generic_set_wptr,
-               }
+               [RADEON_RING_TYPE_GFX_INDEX] = &r100_gfx_ring
        },
        .irq = {
                .set = &r100_irq_set,
@@ -266,19 +269,7 @@ static struct radeon_asic r200_asic = {
                .set_page = &r100_pci_gart_set_page,
        },
        .ring = {
-               [RADEON_RING_TYPE_GFX_INDEX] = {
-                       .ib_execute = &r100_ring_ib_execute,
-                       .emit_fence = &r100_fence_ring_emit,
-                       .emit_semaphore = &r100_semaphore_ring_emit,
-                       .cs_parse = &r100_cs_parse,
-                       .ring_start = &r100_ring_start,
-                       .ring_test = &r100_ring_test,
-                       .ib_test = &r100_ib_test,
-                       .is_lockup = &r100_gpu_is_lockup,
-                       .get_rptr = &radeon_ring_generic_get_rptr,
-                       .get_wptr = &radeon_ring_generic_get_wptr,
-                       .set_wptr = &radeon_ring_generic_set_wptr,
-               }
+               [RADEON_RING_TYPE_GFX_INDEX] = &r100_gfx_ring
        },
        .irq = {
                .set = &r100_irq_set,
@@ -330,6 +321,20 @@ static struct radeon_asic r200_asic = {
        },
 };
 
+static struct radeon_asic_ring r300_gfx_ring = {
+       .ib_execute = &r100_ring_ib_execute,
+       .emit_fence = &r300_fence_ring_emit,
+       .emit_semaphore = &r100_semaphore_ring_emit,
+       .cs_parse = &r300_cs_parse,
+       .ring_start = &r300_ring_start,
+       .ring_test = &r100_ring_test,
+       .ib_test = &r100_ib_test,
+       .is_lockup = &r100_gpu_is_lockup,
+       .get_rptr = &radeon_ring_generic_get_rptr,
+       .get_wptr = &radeon_ring_generic_get_wptr,
+       .set_wptr = &radeon_ring_generic_set_wptr,
+};
+
 static struct radeon_asic r300_asic = {
        .init = &r300_init,
        .fini = &r300_fini,
@@ -345,19 +350,7 @@ static struct radeon_asic r300_asic = {
                .set_page = &r100_pci_gart_set_page,
        },
        .ring = {
-               [RADEON_RING_TYPE_GFX_INDEX] = {
-                       .ib_execute = &r100_ring_ib_execute,
-                       .emit_fence = &r300_fence_ring_emit,
-                       .emit_semaphore = &r100_semaphore_ring_emit,
-                       .cs_parse = &r300_cs_parse,
-                       .ring_start = &r300_ring_start,
-                       .ring_test = &r100_ring_test,
-                       .ib_test = &r100_ib_test,
-                       .is_lockup = &r100_gpu_is_lockup,
-                       .get_rptr = &radeon_ring_generic_get_rptr,
-                       .get_wptr = &radeon_ring_generic_get_wptr,
-                       .set_wptr = &radeon_ring_generic_set_wptr,
-               }
+               [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring
        },
        .irq = {
                .set = &r100_irq_set,
@@ -424,19 +417,7 @@ static struct radeon_asic r300_asic_pcie = {
                .set_page = &rv370_pcie_gart_set_page,
        },
        .ring = {
-               [RADEON_RING_TYPE_GFX_INDEX] = {
-                       .ib_execute = &r100_ring_ib_execute,
-                       .emit_fence = &r300_fence_ring_emit,
-                       .emit_semaphore = &r100_semaphore_ring_emit,
-                       .cs_parse = &r300_cs_parse,
-                       .ring_start = &r300_ring_start,
-                       .ring_test = &r100_ring_test,
-                       .ib_test = &r100_ib_test,
-                       .is_lockup = &r100_gpu_is_lockup,
-                       .get_rptr = &radeon_ring_generic_get_rptr,
-                       .get_wptr = &radeon_ring_generic_get_wptr,
-                       .set_wptr = &radeon_ring_generic_set_wptr,
-               }
+               [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring
        },
        .irq = {
                .set = &r100_irq_set,
@@ -503,19 +484,7 @@ static struct radeon_asic r420_asic = {
                .set_page = &rv370_pcie_gart_set_page,
        },
        .ring = {
-               [RADEON_RING_TYPE_GFX_INDEX] = {
-                       .ib_execute = &r100_ring_ib_execute,
-                       .emit_fence = &r300_fence_ring_emit,
-                       .emit_semaphore = &r100_semaphore_ring_emit,
-                       .cs_parse = &r300_cs_parse,
-                       .ring_start = &r300_ring_start,
-                       .ring_test = &r100_ring_test,
-                       .ib_test = &r100_ib_test,
-                       .is_lockup = &r100_gpu_is_lockup,
-                       .get_rptr = &radeon_ring_generic_get_rptr,
-                       .get_wptr = &radeon_ring_generic_get_wptr,
-                       .set_wptr = &radeon_ring_generic_set_wptr,
-               }
+               [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring
        },
        .irq = {
                .set = &r100_irq_set,
@@ -582,19 +551,7 @@ static struct radeon_asic rs400_asic = {
                .set_page = &rs400_gart_set_page,
        },
        .ring = {
-               [RADEON_RING_TYPE_GFX_INDEX] = {
-                       .ib_execute = &r100_ring_ib_execute,
-                       .emit_fence = &r300_fence_ring_emit,
-                       .emit_semaphore = &r100_semaphore_ring_emit,
-                       .cs_parse = &r300_cs_parse,
-                       .ring_start = &r300_ring_start,
-                       .ring_test = &r100_ring_test,
-                       .ib_test = &r100_ib_test,
-                       .is_lockup = &r100_gpu_is_lockup,
-                       .get_rptr = &radeon_ring_generic_get_rptr,
-                       .get_wptr = &radeon_ring_generic_get_wptr,
-                       .set_wptr = &radeon_ring_generic_set_wptr,
-               }
+               [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring
        },
        .irq = {
                .set = &r100_irq_set,
@@ -661,19 +618,7 @@ static struct radeon_asic rs600_asic = {
                .set_page = &rs600_gart_set_page,
        },
        .ring = {
-               [RADEON_RING_TYPE_GFX_INDEX] = {
-                       .ib_execute = &r100_ring_ib_execute,
-                       .emit_fence = &r300_fence_ring_emit,
-                       .emit_semaphore = &r100_semaphore_ring_emit,
-                       .cs_parse = &r300_cs_parse,
-                       .ring_start = &r300_ring_start,
-                       .ring_test = &r100_ring_test,
-                       .ib_test = &r100_ib_test,
-                       .is_lockup = &r100_gpu_is_lockup,
-                       .get_rptr = &radeon_ring_generic_get_rptr,
-                       .get_wptr = &radeon_ring_generic_get_wptr,
-                       .set_wptr = &radeon_ring_generic_set_wptr,
-               }
+               [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring
        },
        .irq = {
                .set = &rs600_irq_set,
@@ -742,19 +687,7 @@ static struct radeon_asic rs690_asic = {
                .set_page = &rs400_gart_set_page,
        },
        .ring = {
-               [RADEON_RING_TYPE_GFX_INDEX] = {
-                       .ib_execute = &r100_ring_ib_execute,
-                       .emit_fence = &r300_fence_ring_emit,
-                       .emit_semaphore = &r100_semaphore_ring_emit,
-                       .cs_parse = &r300_cs_parse,
-                       .ring_start = &r300_ring_start,
-                       .ring_test = &r100_ring_test,
-                       .ib_test = &r100_ib_test,
-                       .is_lockup = &r100_gpu_is_lockup,
-                       .get_rptr = &radeon_ring_generic_get_rptr,
-                       .get_wptr = &radeon_ring_generic_get_wptr,
-                       .set_wptr = &radeon_ring_generic_set_wptr,
-               }
+               [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring
        },
        .irq = {
                .set = &rs600_irq_set,
@@ -823,19 +756,7 @@ static struct radeon_asic rv515_asic = {
                .set_page = &rv370_pcie_gart_set_page,
        },
        .ring = {
-               [RADEON_RING_TYPE_GFX_INDEX] = {
-                       .ib_execute = &r100_ring_ib_execute,
-                       .emit_fence = &r300_fence_ring_emit,
-                       .emit_semaphore = &r100_semaphore_ring_emit,
-                       .cs_parse = &r300_cs_parse,
-                       .ring_start = &rv515_ring_start,
-                       .ring_test = &r100_ring_test,
-                       .ib_test = &r100_ib_test,
-                       .is_lockup = &r100_gpu_is_lockup,
-                       .get_rptr = &radeon_ring_generic_get_rptr,
-                       .get_wptr = &radeon_ring_generic_get_wptr,
-                       .set_wptr = &radeon_ring_generic_set_wptr,
-               }
+               [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring
        },
        .irq = {
                .set = &rs600_irq_set,
@@ -902,19 +823,7 @@ static struct radeon_asic r520_asic = {
                .set_page = &rv370_pcie_gart_set_page,
        },
        .ring = {
-               [RADEON_RING_TYPE_GFX_INDEX] = {
-                       .ib_execute = &r100_ring_ib_execute,
-                       .emit_fence = &r300_fence_ring_emit,
-                       .emit_semaphore = &r100_semaphore_ring_emit,
-                       .cs_parse = &r300_cs_parse,
-                       .ring_start = &rv515_ring_start,
-                       .ring_test = &r100_ring_test,
-                       .ib_test = &r100_ib_test,
-                       .is_lockup = &r100_gpu_is_lockup,
-                       .get_rptr = &radeon_ring_generic_get_rptr,
-                       .get_wptr = &radeon_ring_generic_get_wptr,
-                       .set_wptr = &radeon_ring_generic_set_wptr,
-               }
+               [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring
        },
        .irq = {
                .set = &rs600_irq_set,
@@ -966,6 +875,32 @@ static struct radeon_asic r520_asic = {
        },
 };
 
+static struct radeon_asic_ring r600_gfx_ring = {
+       .ib_execute = &r600_ring_ib_execute,
+       .emit_fence = &r600_fence_ring_emit,
+       .emit_semaphore = &r600_semaphore_ring_emit,
+       .cs_parse = &r600_cs_parse,
+       .ring_test = &r600_ring_test,
+       .ib_test = &r600_ib_test,
+       .is_lockup = &r600_gfx_is_lockup,
+       .get_rptr = &radeon_ring_generic_get_rptr,
+       .get_wptr = &radeon_ring_generic_get_wptr,
+       .set_wptr = &radeon_ring_generic_set_wptr,
+};
+
+static struct radeon_asic_ring r600_dma_ring = {
+       .ib_execute = &r600_dma_ring_ib_execute,
+       .emit_fence = &r600_dma_fence_ring_emit,
+       .emit_semaphore = &r600_dma_semaphore_ring_emit,
+       .cs_parse = &r600_dma_cs_parse,
+       .ring_test = &r600_dma_ring_test,
+       .ib_test = &r600_dma_ib_test,
+       .is_lockup = &r600_dma_is_lockup,
+       .get_rptr = &radeon_ring_generic_get_rptr,
+       .get_wptr = &radeon_ring_generic_get_wptr,
+       .set_wptr = &radeon_ring_generic_set_wptr,
+};
+
 static struct radeon_asic r600_asic = {
        .init = &r600_init,
        .fini = &r600_fini,
@@ -983,30 +918,8 @@ static struct radeon_asic r600_asic = {
                .set_page = &rs600_gart_set_page,
        },
        .ring = {
-               [RADEON_RING_TYPE_GFX_INDEX] = {
-                       .ib_execute = &r600_ring_ib_execute,
-                       .emit_fence = &r600_fence_ring_emit,
-                       .emit_semaphore = &r600_semaphore_ring_emit,
-                       .cs_parse = &r600_cs_parse,
-                       .ring_test = &r600_ring_test,
-                       .ib_test = &r600_ib_test,
-                       .is_lockup = &r600_gfx_is_lockup,
-                       .get_rptr = &radeon_ring_generic_get_rptr,
-                       .get_wptr = &radeon_ring_generic_get_wptr,
-                       .set_wptr = &radeon_ring_generic_set_wptr,
-               },
-               [R600_RING_TYPE_DMA_INDEX] = {
-                       .ib_execute = &r600_dma_ring_ib_execute,
-                       .emit_fence = &r600_dma_fence_ring_emit,
-                       .emit_semaphore = &r600_dma_semaphore_ring_emit,
-                       .cs_parse = &r600_dma_cs_parse,
-                       .ring_test = &r600_dma_ring_test,
-                       .ib_test = &r600_dma_ib_test,
-                       .is_lockup = &r600_dma_is_lockup,
-                       .get_rptr = &radeon_ring_generic_get_rptr,
-                       .get_wptr = &radeon_ring_generic_get_wptr,
-                       .set_wptr = &radeon_ring_generic_set_wptr,
-               }
+               [RADEON_RING_TYPE_GFX_INDEX] = &r600_gfx_ring,
+               [R600_RING_TYPE_DMA_INDEX] = &r600_dma_ring,
        },
        .irq = {
                .set = &r600_irq_set,
@@ -1078,30 +991,8 @@ static struct radeon_asic rv6xx_asic = {
                .set_page = &rs600_gart_set_page,
        },
        .ring = {
-               [RADEON_RING_TYPE_GFX_INDEX] = {
-                       .ib_execute = &r600_ring_ib_execute,
-                       .emit_fence = &r600_fence_ring_emit,
-                       .emit_semaphore = &r600_semaphore_ring_emit,
-                       .cs_parse = &r600_cs_parse,
-                       .ring_test = &r600_ring_test,
-                       .ib_test = &r600_ib_test,
-                       .is_lockup = &r600_gfx_is_lockup,
-                       .get_rptr = &radeon_ring_generic_get_rptr,
-                       .get_wptr = &radeon_ring_generic_get_wptr,
-                       .set_wptr = &radeon_ring_generic_set_wptr,
-               },
-               [R600_RING_TYPE_DMA_INDEX] = {
-                       .ib_execute = &r600_dma_ring_ib_execute,
-                       .emit_fence = &r600_dma_fence_ring_emit,
-                       .emit_semaphore = &r600_dma_semaphore_ring_emit,
-                       .cs_parse = &r600_dma_cs_parse,
-                       .ring_test = &r600_dma_ring_test,
-                       .ib_test = &r600_dma_ib_test,
-                       .is_lockup = &r600_dma_is_lockup,
-                       .get_rptr = &radeon_ring_generic_get_rptr,
-                       .get_wptr = &radeon_ring_generic_get_wptr,
-                       .set_wptr = &radeon_ring_generic_set_wptr,
-               }
+               [RADEON_RING_TYPE_GFX_INDEX] = &r600_gfx_ring,
+               [R600_RING_TYPE_DMA_INDEX] = &r600_dma_ring,
        },
        .irq = {
                .set = &r600_irq_set,
@@ -1187,30 +1078,8 @@ static struct radeon_asic rs780_asic = {
                .set_page = &rs600_gart_set_page,
        },
        .ring = {
-               [RADEON_RING_TYPE_GFX_INDEX] = {
-                       .ib_execute = &r600_ring_ib_execute,
-                       .emit_fence = &r600_fence_ring_emit,
-                       .emit_semaphore = &r600_semaphore_ring_emit,
-                       .cs_parse = &r600_cs_parse,
-                       .ring_test = &r600_ring_test,
-                       .ib_test = &r600_ib_test,
-                       .is_lockup = &r600_gfx_is_lockup,
-                       .get_rptr = &radeon_ring_generic_get_rptr,
-                       .get_wptr = &radeon_ring_generic_get_wptr,
-                       .set_wptr = &radeon_ring_generic_set_wptr,
-               },
-               [R600_RING_TYPE_DMA_INDEX] = {
-                       .ib_execute = &r600_dma_ring_ib_execute,
-                       .emit_fence = &r600_dma_fence_ring_emit,
-                       .emit_semaphore = &r600_dma_semaphore_ring_emit,
-                       .cs_parse = &r600_dma_cs_parse,
-                       .ring_test = &r600_dma_ring_test,
-                       .ib_test = &r600_dma_ib_test,
-                       .is_lockup = &r600_dma_is_lockup,
-                       .get_rptr = &radeon_ring_generic_get_rptr,
-                       .get_wptr = &radeon_ring_generic_get_wptr,
-                       .set_wptr = &radeon_ring_generic_set_wptr,
-               }
+               [RADEON_RING_TYPE_GFX_INDEX] = &r600_gfx_ring,
+               [R600_RING_TYPE_DMA_INDEX] = &r600_dma_ring,
        },
        .irq = {
                .set = &r600_irq_set,
@@ -1280,6 +1149,19 @@ static struct radeon_asic rs780_asic = {
        },
 };
 
+static struct radeon_asic_ring rv770_uvd_ring = {
+       .ib_execute = &r600_uvd_ib_execute,
+       .emit_fence = &r600_uvd_fence_emit,
+       .emit_semaphore = &r600_uvd_semaphore_emit,
+       .cs_parse = &radeon_uvd_cs_parse,
+       .ring_test = &r600_uvd_ring_test,
+       .ib_test = &r600_uvd_ib_test,
+       .is_lockup = &radeon_ring_test_lockup,
+       .get_rptr = &radeon_ring_generic_get_rptr,
+       .get_wptr = &radeon_ring_generic_get_wptr,
+       .set_wptr = &radeon_ring_generic_set_wptr,
+};
+
 static struct radeon_asic rv770_asic = {
        .init = &rv770_init,
        .fini = &rv770_fini,
@@ -1297,42 +1179,9 @@ static struct radeon_asic rv770_asic = {
                .set_page = &rs600_gart_set_page,
        },
        .ring = {
-               [RADEON_RING_TYPE_GFX_INDEX] = {
-                       .ib_execute = &r600_ring_ib_execute,
-                       .emit_fence = &r600_fence_ring_emit,
-                       .emit_semaphore = &r600_semaphore_ring_emit,
-                       .cs_parse = &r600_cs_parse,
-                       .ring_test = &r600_ring_test,
-                       .ib_test = &r600_ib_test,
-                       .is_lockup = &r600_gfx_is_lockup,
-                       .get_rptr = &radeon_ring_generic_get_rptr,
-                       .get_wptr = &radeon_ring_generic_get_wptr,
-                       .set_wptr = &radeon_ring_generic_set_wptr,
-               },
-               [R600_RING_TYPE_DMA_INDEX] = {
-                       .ib_execute = &r600_dma_ring_ib_execute,
-                       .emit_fence = &r600_dma_fence_ring_emit,
-                       .emit_semaphore = &r600_dma_semaphore_ring_emit,
-                       .cs_parse = &r600_dma_cs_parse,
-                       .ring_test = &r600_dma_ring_test,
-                       .ib_test = &r600_dma_ib_test,
-                       .is_lockup = &r600_dma_is_lockup,
-                       .get_rptr = &radeon_ring_generic_get_rptr,
-                       .get_wptr = &radeon_ring_generic_get_wptr,
-                       .set_wptr = &radeon_ring_generic_set_wptr,
-               },
-               [R600_RING_TYPE_UVD_INDEX] = {
-                       .ib_execute = &r600_uvd_ib_execute,
-                       .emit_fence = &r600_uvd_fence_emit,
-                       .emit_semaphore = &r600_uvd_semaphore_emit,
-                       .cs_parse = &radeon_uvd_cs_parse,
-                       .ring_test = &r600_uvd_ring_test,
-                       .ib_test = &r600_uvd_ib_test,
-                       .is_lockup = &radeon_ring_test_lockup,
-                       .get_rptr = &radeon_ring_generic_get_rptr,
-                       .get_wptr = &radeon_ring_generic_get_wptr,
-                       .set_wptr = &radeon_ring_generic_set_wptr,
-               }
+               [RADEON_RING_TYPE_GFX_INDEX] = &r600_gfx_ring,
+               [R600_RING_TYPE_DMA_INDEX] = &r600_dma_ring,
+               [R600_RING_TYPE_UVD_INDEX] = &rv770_uvd_ring,
        },
        .irq = {
                .set = &r600_irq_set,
@@ -1405,6 +1254,32 @@ static struct radeon_asic rv770_asic = {
        },
 };
 
+static struct radeon_asic_ring evergreen_gfx_ring = {
+       .ib_execute = &evergreen_ring_ib_execute,
+       .emit_fence = &r600_fence_ring_emit,
+       .emit_semaphore = &r600_semaphore_ring_emit,
+       .cs_parse = &evergreen_cs_parse,
+       .ring_test = &r600_ring_test,
+       .ib_test = &r600_ib_test,
+       .is_lockup = &evergreen_gfx_is_lockup,
+       .get_rptr = &radeon_ring_generic_get_rptr,
+       .get_wptr = &radeon_ring_generic_get_wptr,
+       .set_wptr = &radeon_ring_generic_set_wptr,
+};
+
+static struct radeon_asic_ring evergreen_dma_ring = {
+       .ib_execute = &evergreen_dma_ring_ib_execute,
+       .emit_fence = &evergreen_dma_fence_ring_emit,
+       .emit_semaphore = &r600_dma_semaphore_ring_emit,
+       .cs_parse = &evergreen_dma_cs_parse,
+       .ring_test = &r600_dma_ring_test,
+       .ib_test = &r600_dma_ib_test,
+       .is_lockup = &evergreen_dma_is_lockup,
+       .get_rptr = &radeon_ring_generic_get_rptr,
+       .get_wptr = &radeon_ring_generic_get_wptr,
+       .set_wptr = &radeon_ring_generic_set_wptr,
+};
+
 static struct radeon_asic evergreen_asic = {
        .init = &evergreen_init,
        .fini = &evergreen_fini,
@@ -1422,42 +1297,9 @@ static struct radeon_asic evergreen_asic = {
                .set_page = &rs600_gart_set_page,
        },
        .ring = {
-               [RADEON_RING_TYPE_GFX_INDEX] = {
-                       .ib_execute = &evergreen_ring_ib_execute,
-                       .emit_fence = &r600_fence_ring_emit,
-                       .emit_semaphore = &r600_semaphore_ring_emit,
-                       .cs_parse = &evergreen_cs_parse,
-                       .ring_test = &r600_ring_test,
-                       .ib_test = &r600_ib_test,
-                       .is_lockup = &evergreen_gfx_is_lockup,
-                       .get_rptr = &radeon_ring_generic_get_rptr,
-                       .get_wptr = &radeon_ring_generic_get_wptr,
-                       .set_wptr = &radeon_ring_generic_set_wptr,
-               },
-               [R600_RING_TYPE_DMA_INDEX] = {
-                       .ib_execute = &evergreen_dma_ring_ib_execute,
-                       .emit_fence = &evergreen_dma_fence_ring_emit,
-                       .emit_semaphore = &r600_dma_semaphore_ring_emit,
-                       .cs_parse = &evergreen_dma_cs_parse,
-                       .ring_test = &r600_dma_ring_test,
-                       .ib_test = &r600_dma_ib_test,
-                       .is_lockup = &evergreen_dma_is_lockup,
-                       .get_rptr = &radeon_ring_generic_get_rptr,
-                       .get_wptr = &radeon_ring_generic_get_wptr,
-                       .set_wptr = &radeon_ring_generic_set_wptr,
-               },
-               [R600_RING_TYPE_UVD_INDEX] = {
-                       .ib_execute = &r600_uvd_ib_execute,
-                       .emit_fence = &r600_uvd_fence_emit,
-                       .emit_semaphore = &r600_uvd_semaphore_emit,
-                       .cs_parse = &radeon_uvd_cs_parse,
-                       .ring_test = &r600_uvd_ring_test,
-                       .ib_test = &r600_uvd_ib_test,
-                       .is_lockup = &radeon_ring_test_lockup,
-                       .get_rptr = &radeon_ring_generic_get_rptr,
-                       .get_wptr = &radeon_ring_generic_get_wptr,
-                       .set_wptr = &radeon_ring_generic_set_wptr,
-               }
+               [RADEON_RING_TYPE_GFX_INDEX] = &evergreen_gfx_ring,
+               [R600_RING_TYPE_DMA_INDEX] = &evergreen_dma_ring,
+               [R600_RING_TYPE_UVD_INDEX] = &rv770_uvd_ring,
        },
        .irq = {
                .set = &evergreen_irq_set,
@@ -1547,42 +1389,9 @@ static struct radeon_asic sumo_asic = {
                .set_page = &rs600_gart_set_page,
        },
        .ring = {
-               [RADEON_RING_TYPE_GFX_INDEX] = {
-                       .ib_execute = &evergreen_ring_ib_execute,
-                       .emit_fence = &r600_fence_ring_emit,
-                       .emit_semaphore = &r600_semaphore_ring_emit,
-                       .cs_parse = &evergreen_cs_parse,
-                       .ring_test = &r600_ring_test,
-                       .ib_test = &r600_ib_test,
-                       .is_lockup = &evergreen_gfx_is_lockup,
-                       .get_rptr = &radeon_ring_generic_get_rptr,
-                       .get_wptr = &radeon_ring_generic_get_wptr,
-                       .set_wptr = &radeon_ring_generic_set_wptr,
-               },
-               [R600_RING_TYPE_DMA_INDEX] = {
-                       .ib_execute = &evergreen_dma_ring_ib_execute,
-                       .emit_fence = &evergreen_dma_fence_ring_emit,
-                       .emit_semaphore = &r600_dma_semaphore_ring_emit,
-                       .cs_parse = &evergreen_dma_cs_parse,
-                       .ring_test = &r600_dma_ring_test,
-                       .ib_test = &r600_dma_ib_test,
-                       .is_lockup = &evergreen_dma_is_lockup,
-                       .get_rptr = &radeon_ring_generic_get_rptr,
-                       .get_wptr = &radeon_ring_generic_get_wptr,
-                       .set_wptr = &radeon_ring_generic_set_wptr,
-               },
-               [R600_RING_TYPE_UVD_INDEX] = {
-                       .ib_execute = &r600_uvd_ib_execute,
-                       .emit_fence = &r600_uvd_fence_emit,
-                       .emit_semaphore = &r600_uvd_semaphore_emit,
-                       .cs_parse = &radeon_uvd_cs_parse,
-                       .ring_test = &r600_uvd_ring_test,
-                       .ib_test = &r600_uvd_ib_test,
-                       .is_lockup = &radeon_ring_test_lockup,
-                       .get_rptr = &radeon_ring_generic_get_rptr,
-                       .get_wptr = &radeon_ring_generic_get_wptr,
-                       .set_wptr = &radeon_ring_generic_set_wptr,
-               }
+               [RADEON_RING_TYPE_GFX_INDEX] = &evergreen_gfx_ring,
+               [R600_RING_TYPE_DMA_INDEX] = &evergreen_dma_ring,
+               [R600_RING_TYPE_UVD_INDEX] = &rv770_uvd_ring,
        },
        .irq = {
                .set = &evergreen_irq_set,
@@ -1671,42 +1480,9 @@ static struct radeon_asic btc_asic = {
                .set_page = &rs600_gart_set_page,
        },
        .ring = {
-               [RADEON_RING_TYPE_GFX_INDEX] = {
-                       .ib_execute = &evergreen_ring_ib_execute,
-                       .emit_fence = &r600_fence_ring_emit,
-                       .emit_semaphore = &r600_semaphore_ring_emit,
-                       .cs_parse = &evergreen_cs_parse,
-                       .ring_test = &r600_ring_test,
-                       .ib_test = &r600_ib_test,
-                       .is_lockup = &evergreen_gfx_is_lockup,
-                       .get_rptr = &radeon_ring_generic_get_rptr,
-                       .get_wptr = &radeon_ring_generic_get_wptr,
-                       .set_wptr = &radeon_ring_generic_set_wptr,
-               },
-               [R600_RING_TYPE_DMA_INDEX] = {
-                       .ib_execute = &evergreen_dma_ring_ib_execute,
-                       .emit_fence = &evergreen_dma_fence_ring_emit,
-                       .emit_semaphore = &r600_dma_semaphore_ring_emit,
-                       .cs_parse = &evergreen_dma_cs_parse,
-                       .ring_test = &r600_dma_ring_test,
-                       .ib_test = &r600_dma_ib_test,
-                       .is_lockup = &evergreen_dma_is_lockup,
-                       .get_rptr = &radeon_ring_generic_get_rptr,
-                       .get_wptr = &radeon_ring_generic_get_wptr,
-                       .set_wptr = &radeon_ring_generic_set_wptr,
-               },
-               [R600_RING_TYPE_UVD_INDEX] = {
-                       .ib_execute = &r600_uvd_ib_execute,
-                       .emit_fence = &r600_uvd_fence_emit,
-                       .emit_semaphore = &r600_uvd_semaphore_emit,
-                       .cs_parse = &radeon_uvd_cs_parse,
-                       .ring_test = &r600_uvd_ring_test,
-                       .ib_test = &r600_uvd_ib_test,
-                       .is_lockup = &radeon_ring_test_lockup,
-                       .get_rptr = &radeon_ring_generic_get_rptr,
-                       .get_wptr = &radeon_ring_generic_get_wptr,
-                       .set_wptr = &radeon_ring_generic_set_wptr,
-               }
+               [RADEON_RING_TYPE_GFX_INDEX] = &evergreen_gfx_ring,
+               [R600_RING_TYPE_DMA_INDEX] = &evergreen_dma_ring,
+               [R600_RING_TYPE_UVD_INDEX] = &rv770_uvd_ring,
        },
        .irq = {
                .set = &evergreen_irq_set,
@@ -1779,6 +1555,49 @@ static struct radeon_asic btc_asic = {
        },
 };
 
+static struct radeon_asic_ring cayman_gfx_ring = {
+       .ib_execute = &cayman_ring_ib_execute,
+       .ib_parse = &evergreen_ib_parse,
+       .emit_fence = &cayman_fence_ring_emit,
+       .emit_semaphore = &r600_semaphore_ring_emit,
+       .cs_parse = &evergreen_cs_parse,
+       .ring_test = &r600_ring_test,
+       .ib_test = &r600_ib_test,
+       .is_lockup = &cayman_gfx_is_lockup,
+       .vm_flush = &cayman_vm_flush,
+       .get_rptr = &radeon_ring_generic_get_rptr,
+       .get_wptr = &radeon_ring_generic_get_wptr,
+       .set_wptr = &radeon_ring_generic_set_wptr,
+};
+
+static struct radeon_asic_ring cayman_dma_ring = {
+       .ib_execute = &cayman_dma_ring_ib_execute,
+       .ib_parse = &evergreen_dma_ib_parse,
+       .emit_fence = &evergreen_dma_fence_ring_emit,
+       .emit_semaphore = &r600_dma_semaphore_ring_emit,
+       .cs_parse = &evergreen_dma_cs_parse,
+       .ring_test = &r600_dma_ring_test,
+       .ib_test = &r600_dma_ib_test,
+       .is_lockup = &cayman_dma_is_lockup,
+       .vm_flush = &cayman_dma_vm_flush,
+       .get_rptr = &radeon_ring_generic_get_rptr,
+       .get_wptr = &radeon_ring_generic_get_wptr,
+       .set_wptr = &radeon_ring_generic_set_wptr
+};
+
+static struct radeon_asic_ring cayman_uvd_ring = {
+       .ib_execute = &r600_uvd_ib_execute,
+       .emit_fence = &r600_uvd_fence_emit,
+       .emit_semaphore = &cayman_uvd_semaphore_emit,
+       .cs_parse = &radeon_uvd_cs_parse,
+       .ring_test = &r600_uvd_ring_test,
+       .ib_test = &r600_uvd_ib_test,
+       .is_lockup = &radeon_ring_test_lockup,
+       .get_rptr = &radeon_ring_generic_get_rptr,
+       .get_wptr = &radeon_ring_generic_get_wptr,
+       .set_wptr = &radeon_ring_generic_set_wptr,
+};
+
 static struct radeon_asic cayman_asic = {
        .init = &cayman_init,
        .fini = &cayman_fini,
@@ -1802,88 +1621,12 @@ static struct radeon_asic cayman_asic = {
                .set_page = &cayman_vm_set_page,
        },
        .ring = {
-               [RADEON_RING_TYPE_GFX_INDEX] = {
-                       .ib_execute = &cayman_ring_ib_execute,
-                       .ib_parse = &evergreen_ib_parse,
-                       .emit_fence = &cayman_fence_ring_emit,
-                       .emit_semaphore = &r600_semaphore_ring_emit,
-                       .cs_parse = &evergreen_cs_parse,
-                       .ring_test = &r600_ring_test,
-                       .ib_test = &r600_ib_test,
-                       .is_lockup = &cayman_gfx_is_lockup,
-                       .vm_flush = &cayman_vm_flush,
-                       .get_rptr = &radeon_ring_generic_get_rptr,
-                       .get_wptr = &radeon_ring_generic_get_wptr,
-                       .set_wptr = &radeon_ring_generic_set_wptr,
-               },
-               [CAYMAN_RING_TYPE_CP1_INDEX] = {
-                       .ib_execute = &cayman_ring_ib_execute,
-                       .ib_parse = &evergreen_ib_parse,
-                       .emit_fence = &cayman_fence_ring_emit,
-                       .emit_semaphore = &r600_semaphore_ring_emit,
-                       .cs_parse = &evergreen_cs_parse,
-                       .ring_test = &r600_ring_test,
-                       .ib_test = &r600_ib_test,
-                       .is_lockup = &cayman_gfx_is_lockup,
-                       .vm_flush = &cayman_vm_flush,
-                       .get_rptr = &radeon_ring_generic_get_rptr,
-                       .get_wptr = &radeon_ring_generic_get_wptr,
-                       .set_wptr = &radeon_ring_generic_set_wptr,
-               },
-               [CAYMAN_RING_TYPE_CP2_INDEX] = {
-                       .ib_execute = &cayman_ring_ib_execute,
-                       .ib_parse = &evergreen_ib_parse,
-                       .emit_fence = &cayman_fence_ring_emit,
-                       .emit_semaphore = &r600_semaphore_ring_emit,
-                       .cs_parse = &evergreen_cs_parse,
-                       .ring_test = &r600_ring_test,
-                       .ib_test = &r600_ib_test,
-                       .is_lockup = &cayman_gfx_is_lockup,
-                       .vm_flush = &cayman_vm_flush,
-                       .get_rptr = &radeon_ring_generic_get_rptr,
-                       .get_wptr = &radeon_ring_generic_get_wptr,
-                       .set_wptr = &radeon_ring_generic_set_wptr,
-               },
-               [R600_RING_TYPE_DMA_INDEX] = {
-                       .ib_execute = &cayman_dma_ring_ib_execute,
-                       .ib_parse = &evergreen_dma_ib_parse,
-                       .emit_fence = &evergreen_dma_fence_ring_emit,
-                       .emit_semaphore = &r600_dma_semaphore_ring_emit,
-                       .cs_parse = &evergreen_dma_cs_parse,
-                       .ring_test = &r600_dma_ring_test,
-                       .ib_test = &r600_dma_ib_test,
-                       .is_lockup = &cayman_dma_is_lockup,
-                       .vm_flush = &cayman_dma_vm_flush,
-                       .get_rptr = &radeon_ring_generic_get_rptr,
-                       .get_wptr = &radeon_ring_generic_get_wptr,
-                       .set_wptr = &radeon_ring_generic_set_wptr,
-               },
-               [CAYMAN_RING_TYPE_DMA1_INDEX] = {
-                       .ib_execute = &cayman_dma_ring_ib_execute,
-                       .ib_parse = &evergreen_dma_ib_parse,
-                       .emit_fence = &evergreen_dma_fence_ring_emit,
-                       .emit_semaphore = &r600_dma_semaphore_ring_emit,
-                       .cs_parse = &evergreen_dma_cs_parse,
-                       .ring_test = &r600_dma_ring_test,
-                       .ib_test = &r600_dma_ib_test,
-                       .is_lockup = &cayman_dma_is_lockup,
-                       .vm_flush = &cayman_dma_vm_flush,
-                       .get_rptr = &radeon_ring_generic_get_rptr,
-                       .get_wptr = &radeon_ring_generic_get_wptr,
-                       .set_wptr = &radeon_ring_generic_set_wptr,
-               },
-               [R600_RING_TYPE_UVD_INDEX] = {
-                       .ib_execute = &r600_uvd_ib_execute,
-                       .emit_fence = &r600_uvd_fence_emit,
-                       .emit_semaphore = &cayman_uvd_semaphore_emit,
-                       .cs_parse = &radeon_uvd_cs_parse,
-                       .ring_test = &r600_uvd_ring_test,
-                       .ib_test = &r600_uvd_ib_test,
-                       .is_lockup = &radeon_ring_test_lockup,
-                       .get_rptr = &radeon_ring_generic_get_rptr,
-                       .get_wptr = &radeon_ring_generic_get_wptr,
-                       .set_wptr = &radeon_ring_generic_set_wptr,
-               }
+               [RADEON_RING_TYPE_GFX_INDEX] = &cayman_gfx_ring,
+               [CAYMAN_RING_TYPE_CP1_INDEX] = &cayman_gfx_ring,
+               [CAYMAN_RING_TYPE_CP2_INDEX] = &cayman_gfx_ring,
+               [R600_RING_TYPE_DMA_INDEX] = &cayman_dma_ring,
+               [CAYMAN_RING_TYPE_DMA1_INDEX] = &cayman_dma_ring,
+               [R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring,
        },
        .irq = {
                .set = &evergreen_irq_set,
@@ -1979,88 +1722,12 @@ static struct radeon_asic trinity_asic = {
                .set_page = &cayman_vm_set_page,
        },
        .ring = {
-               [RADEON_RING_TYPE_GFX_INDEX] = {
-                       .ib_execute = &cayman_ring_ib_execute,
-                       .ib_parse = &evergreen_ib_parse,
-                       .emit_fence = &cayman_fence_ring_emit,
-                       .emit_semaphore = &r600_semaphore_ring_emit,
-                       .cs_parse = &evergreen_cs_parse,
-                       .ring_test = &r600_ring_test,
-                       .ib_test = &r600_ib_test,
-                       .is_lockup = &cayman_gfx_is_lockup,
-                       .vm_flush = &cayman_vm_flush,
-                       .get_rptr = &radeon_ring_generic_get_rptr,
-                       .get_wptr = &radeon_ring_generic_get_wptr,
-                       .set_wptr = &radeon_ring_generic_set_wptr,
-               },
-               [CAYMAN_RING_TYPE_CP1_INDEX] = {
-                       .ib_execute = &cayman_ring_ib_execute,
-                       .ib_parse = &evergreen_ib_parse,
-                       .emit_fence = &cayman_fence_ring_emit,
-                       .emit_semaphore = &r600_semaphore_ring_emit,
-                       .cs_parse = &evergreen_cs_parse,
-                       .ring_test = &r600_ring_test,
-                       .ib_test = &r600_ib_test,
-                       .is_lockup = &cayman_gfx_is_lockup,
-                       .vm_flush = &cayman_vm_flush,
-                       .get_rptr = &radeon_ring_generic_get_rptr,
-                       .get_wptr = &radeon_ring_generic_get_wptr,
-                       .set_wptr = &radeon_ring_generic_set_wptr,
-               },
-               [CAYMAN_RING_TYPE_CP2_INDEX] = {
-                       .ib_execute = &cayman_ring_ib_execute,
-                       .ib_parse = &evergreen_ib_parse,
-                       .emit_fence = &cayman_fence_ring_emit,
-                       .emit_semaphore = &r600_semaphore_ring_emit,
-                       .cs_parse = &evergreen_cs_parse,
-                       .ring_test = &r600_ring_test,
-                       .ib_test = &r600_ib_test,
-                       .is_lockup = &cayman_gfx_is_lockup,
-                       .vm_flush = &cayman_vm_flush,
-                       .get_rptr = &radeon_ring_generic_get_rptr,
-                       .get_wptr = &radeon_ring_generic_get_wptr,
-                       .set_wptr = &radeon_ring_generic_set_wptr,
-               },
-               [R600_RING_TYPE_DMA_INDEX] = {
-                       .ib_execute = &cayman_dma_ring_ib_execute,
-                       .ib_parse = &evergreen_dma_ib_parse,
-                       .emit_fence = &evergreen_dma_fence_ring_emit,
-                       .emit_semaphore = &r600_dma_semaphore_ring_emit,
-                       .cs_parse = &evergreen_dma_cs_parse,
-                       .ring_test = &r600_dma_ring_test,
-                       .ib_test = &r600_dma_ib_test,
-                       .is_lockup = &cayman_dma_is_lockup,
-                       .vm_flush = &cayman_dma_vm_flush,
-                       .get_rptr = &radeon_ring_generic_get_rptr,
-                       .get_wptr = &radeon_ring_generic_get_wptr,
-                       .set_wptr = &radeon_ring_generic_set_wptr,
-               },
-               [CAYMAN_RING_TYPE_DMA1_INDEX] = {
-                       .ib_execute = &cayman_dma_ring_ib_execute,
-                       .ib_parse = &evergreen_dma_ib_parse,
-                       .emit_fence = &evergreen_dma_fence_ring_emit,
-                       .emit_semaphore = &r600_dma_semaphore_ring_emit,
-                       .cs_parse = &evergreen_dma_cs_parse,
-                       .ring_test = &r600_dma_ring_test,
-                       .ib_test = &r600_dma_ib_test,
-                       .is_lockup = &cayman_dma_is_lockup,
-                       .vm_flush = &cayman_dma_vm_flush,
-                       .get_rptr = &radeon_ring_generic_get_rptr,
-                       .get_wptr = &radeon_ring_generic_get_wptr,
-                       .set_wptr = &radeon_ring_generic_set_wptr,
-               },
-               [R600_RING_TYPE_UVD_INDEX] = {
-                       .ib_execute = &r600_uvd_ib_execute,
-                       .emit_fence = &r600_uvd_fence_emit,
-                       .emit_semaphore = &cayman_uvd_semaphore_emit,
-                       .cs_parse = &radeon_uvd_cs_parse,
-                       .ring_test = &r600_uvd_ring_test,
-                       .ib_test = &r600_uvd_ib_test,
-                       .is_lockup = &radeon_ring_test_lockup,
-                       .get_rptr = &radeon_ring_generic_get_rptr,
-                       .get_wptr = &radeon_ring_generic_get_wptr,
-                       .set_wptr = &radeon_ring_generic_set_wptr,
-               }
+               [RADEON_RING_TYPE_GFX_INDEX] = &cayman_gfx_ring,
+               [CAYMAN_RING_TYPE_CP1_INDEX] = &cayman_gfx_ring,
+               [CAYMAN_RING_TYPE_CP2_INDEX] = &cayman_gfx_ring,
+               [R600_RING_TYPE_DMA_INDEX] = &cayman_dma_ring,
+               [CAYMAN_RING_TYPE_DMA1_INDEX] = &cayman_dma_ring,
+               [R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring,
        },
        .irq = {
                .set = &evergreen_irq_set,
@@ -2130,6 +1797,36 @@ static struct radeon_asic trinity_asic = {
        },
 };
 
+static struct radeon_asic_ring si_gfx_ring = {
+       .ib_execute = &si_ring_ib_execute,
+       .ib_parse = &si_ib_parse,
+       .emit_fence = &si_fence_ring_emit,
+       .emit_semaphore = &r600_semaphore_ring_emit,
+       .cs_parse = NULL,
+       .ring_test = &r600_ring_test,
+       .ib_test = &r600_ib_test,
+       .is_lockup = &si_gfx_is_lockup,
+       .vm_flush = &si_vm_flush,
+       .get_rptr = &radeon_ring_generic_get_rptr,
+       .get_wptr = &radeon_ring_generic_get_wptr,
+       .set_wptr = &radeon_ring_generic_set_wptr,
+};
+
+static struct radeon_asic_ring si_dma_ring = {
+       .ib_execute = &cayman_dma_ring_ib_execute,
+       .ib_parse = &evergreen_dma_ib_parse,
+       .emit_fence = &evergreen_dma_fence_ring_emit,
+       .emit_semaphore = &r600_dma_semaphore_ring_emit,
+       .cs_parse = NULL,
+       .ring_test = &r600_dma_ring_test,
+       .ib_test = &r600_dma_ib_test,
+       .is_lockup = &si_dma_is_lockup,
+       .vm_flush = &si_dma_vm_flush,
+       .get_rptr = &radeon_ring_generic_get_rptr,
+       .get_wptr = &radeon_ring_generic_get_wptr,
+       .set_wptr = &radeon_ring_generic_set_wptr,
+};
+
 static struct radeon_asic si_asic = {
        .init = &si_init,
        .fini = &si_fini,
@@ -2153,88 +1850,12 @@ static struct radeon_asic si_asic = {
                .set_page = &si_vm_set_page,
        },
        .ring = {
-               [RADEON_RING_TYPE_GFX_INDEX] = {
-                       .ib_execute = &si_ring_ib_execute,
-                       .ib_parse = &si_ib_parse,
-                       .emit_fence = &si_fence_ring_emit,
-                       .emit_semaphore = &r600_semaphore_ring_emit,
-                       .cs_parse = NULL,
-                       .ring_test = &r600_ring_test,
-                       .ib_test = &r600_ib_test,
-                       .is_lockup = &si_gfx_is_lockup,
-                       .vm_flush = &si_vm_flush,
-                       .get_rptr = &radeon_ring_generic_get_rptr,
-                       .get_wptr = &radeon_ring_generic_get_wptr,
-                       .set_wptr = &radeon_ring_generic_set_wptr,
-               },
-               [CAYMAN_RING_TYPE_CP1_INDEX] = {
-                       .ib_execute = &si_ring_ib_execute,
-                       .ib_parse = &si_ib_parse,
-                       .emit_fence = &si_fence_ring_emit,
-                       .emit_semaphore = &r600_semaphore_ring_emit,
-                       .cs_parse = NULL,
-                       .ring_test = &r600_ring_test,
-                       .ib_test = &r600_ib_test,
-                       .is_lockup = &si_gfx_is_lockup,
-                       .vm_flush = &si_vm_flush,
-                       .get_rptr = &radeon_ring_generic_get_rptr,
-                       .get_wptr = &radeon_ring_generic_get_wptr,
-                       .set_wptr = &radeon_ring_generic_set_wptr,
-               },
-               [CAYMAN_RING_TYPE_CP2_INDEX] = {
-                       .ib_execute = &si_ring_ib_execute,
-                       .ib_parse = &si_ib_parse,
-                       .emit_fence = &si_fence_ring_emit,
-                       .emit_semaphore = &r600_semaphore_ring_emit,
-                       .cs_parse = NULL,
-                       .ring_test = &r600_ring_test,
-                       .ib_test = &r600_ib_test,
-                       .is_lockup = &si_gfx_is_lockup,
-                       .vm_flush = &si_vm_flush,
-                       .get_rptr = &radeon_ring_generic_get_rptr,
-                       .get_wptr = &radeon_ring_generic_get_wptr,
-                       .set_wptr = &radeon_ring_generic_set_wptr,
-               },
-               [R600_RING_TYPE_DMA_INDEX] = {
-                       .ib_execute = &cayman_dma_ring_ib_execute,
-                       .ib_parse = &evergreen_dma_ib_parse,
-                       .emit_fence = &evergreen_dma_fence_ring_emit,
-                       .emit_semaphore = &r600_dma_semaphore_ring_emit,
-                       .cs_parse = NULL,
-                       .ring_test = &r600_dma_ring_test,
-                       .ib_test = &r600_dma_ib_test,
-                       .is_lockup = &si_dma_is_lockup,
-                       .vm_flush = &si_dma_vm_flush,
-                       .get_rptr = &radeon_ring_generic_get_rptr,
-                       .get_wptr = &radeon_ring_generic_get_wptr,
-                       .set_wptr = &radeon_ring_generic_set_wptr,
-               },
-               [CAYMAN_RING_TYPE_DMA1_INDEX] = {
-                       .ib_execute = &cayman_dma_ring_ib_execute,
-                       .ib_parse = &evergreen_dma_ib_parse,
-                       .emit_fence = &evergreen_dma_fence_ring_emit,
-                       .emit_semaphore = &r600_dma_semaphore_ring_emit,
-                       .cs_parse = NULL,
-                       .ring_test = &r600_dma_ring_test,
-                       .ib_test = &r600_dma_ib_test,
-                       .is_lockup = &si_dma_is_lockup,
-                       .vm_flush = &si_dma_vm_flush,
-                       .get_rptr = &radeon_ring_generic_get_rptr,
-                       .get_wptr = &radeon_ring_generic_get_wptr,
-                       .set_wptr = &radeon_ring_generic_set_wptr,
-               },
-               [R600_RING_TYPE_UVD_INDEX] = {
-                       .ib_execute = &r600_uvd_ib_execute,
-                       .emit_fence = &r600_uvd_fence_emit,
-                       .emit_semaphore = &cayman_uvd_semaphore_emit,
-                       .cs_parse = &radeon_uvd_cs_parse,
-                       .ring_test = &r600_uvd_ring_test,
-                       .ib_test = &r600_uvd_ib_test,
-                       .is_lockup = &radeon_ring_test_lockup,
-                       .get_rptr = &radeon_ring_generic_get_rptr,
-                       .get_wptr = &radeon_ring_generic_get_wptr,
-                       .set_wptr = &radeon_ring_generic_set_wptr,
-               }
+               [RADEON_RING_TYPE_GFX_INDEX] = &si_gfx_ring,
+               [CAYMAN_RING_TYPE_CP1_INDEX] = &si_gfx_ring,
+               [CAYMAN_RING_TYPE_CP2_INDEX] = &si_gfx_ring,
+               [R600_RING_TYPE_DMA_INDEX] = &si_dma_ring,
+               [CAYMAN_RING_TYPE_DMA1_INDEX] = &si_dma_ring,
+               [R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring,
        },
        .irq = {
                .set = &si_irq_set,
@@ -2305,6 +1926,51 @@ static struct radeon_asic si_asic = {
        },
 };
 
+static struct radeon_asic_ring ci_gfx_ring = {
+       .ib_execute = &cik_ring_ib_execute,
+       .ib_parse = &cik_ib_parse,
+       .emit_fence = &cik_fence_gfx_ring_emit,
+       .emit_semaphore = &cik_semaphore_ring_emit,
+       .cs_parse = NULL,
+       .ring_test = &cik_ring_test,
+       .ib_test = &cik_ib_test,
+       .is_lockup = &cik_gfx_is_lockup,
+       .vm_flush = &cik_vm_flush,
+       .get_rptr = &radeon_ring_generic_get_rptr,
+       .get_wptr = &radeon_ring_generic_get_wptr,
+       .set_wptr = &radeon_ring_generic_set_wptr,
+};
+
+static struct radeon_asic_ring ci_cp_ring = {
+       .ib_execute = &cik_ring_ib_execute,
+       .ib_parse = &cik_ib_parse,
+       .emit_fence = &cik_fence_compute_ring_emit,
+       .emit_semaphore = &cik_semaphore_ring_emit,
+       .cs_parse = NULL,
+       .ring_test = &cik_ring_test,
+       .ib_test = &cik_ib_test,
+       .is_lockup = &cik_gfx_is_lockup,
+       .vm_flush = &cik_vm_flush,
+       .get_rptr = &cik_compute_ring_get_rptr,
+       .get_wptr = &cik_compute_ring_get_wptr,
+       .set_wptr = &cik_compute_ring_set_wptr,
+};
+
+static struct radeon_asic_ring ci_dma_ring = {
+       .ib_execute = &cik_sdma_ring_ib_execute,
+       .ib_parse = &cik_ib_parse,
+       .emit_fence = &cik_sdma_fence_ring_emit,
+       .emit_semaphore = &cik_sdma_semaphore_ring_emit,
+       .cs_parse = NULL,
+       .ring_test = &cik_sdma_ring_test,
+       .ib_test = &cik_sdma_ib_test,
+       .is_lockup = &cik_sdma_is_lockup,
+       .vm_flush = &cik_dma_vm_flush,
+       .get_rptr = &radeon_ring_generic_get_rptr,
+       .get_wptr = &radeon_ring_generic_get_wptr,
+       .set_wptr = &radeon_ring_generic_set_wptr,
+};
+
 static struct radeon_asic ci_asic = {
        .init = &cik_init,
        .fini = &cik_fini,
@@ -2328,88 +1994,12 @@ static struct radeon_asic ci_asic = {
                .set_page = &cik_vm_set_page,
        },
        .ring = {
-               [RADEON_RING_TYPE_GFX_INDEX] = {
-                       .ib_execute = &cik_ring_ib_execute,
-                       .ib_parse = &cik_ib_parse,
-                       .emit_fence = &cik_fence_gfx_ring_emit,
-                       .emit_semaphore = &cik_semaphore_ring_emit,
-                       .cs_parse = NULL,
-                       .ring_test = &cik_ring_test,
-                       .ib_test = &cik_ib_test,
-                       .is_lockup = &cik_gfx_is_lockup,
-                       .vm_flush = &cik_vm_flush,
-                       .get_rptr = &radeon_ring_generic_get_rptr,
-                       .get_wptr = &radeon_ring_generic_get_wptr,
-                       .set_wptr = &radeon_ring_generic_set_wptr,
-               },
-               [CAYMAN_RING_TYPE_CP1_INDEX] = {
-                       .ib_execute = &cik_ring_ib_execute,
-                       .ib_parse = &cik_ib_parse,
-                       .emit_fence = &cik_fence_compute_ring_emit,
-                       .emit_semaphore = &cik_semaphore_ring_emit,
-                       .cs_parse = NULL,
-                       .ring_test = &cik_ring_test,
-                       .ib_test = &cik_ib_test,
-                       .is_lockup = &cik_gfx_is_lockup,
-                       .vm_flush = &cik_vm_flush,
-                       .get_rptr = &cik_compute_ring_get_rptr,
-                       .get_wptr = &cik_compute_ring_get_wptr,
-                       .set_wptr = &cik_compute_ring_set_wptr,
-               },
-               [CAYMAN_RING_TYPE_CP2_INDEX] = {
-                       .ib_execute = &cik_ring_ib_execute,
-                       .ib_parse = &cik_ib_parse,
-                       .emit_fence = &cik_fence_compute_ring_emit,
-                       .emit_semaphore = &cik_semaphore_ring_emit,
-                       .cs_parse = NULL,
-                       .ring_test = &cik_ring_test,
-                       .ib_test = &cik_ib_test,
-                       .is_lockup = &cik_gfx_is_lockup,
-                       .vm_flush = &cik_vm_flush,
-                       .get_rptr = &cik_compute_ring_get_rptr,
-                       .get_wptr = &cik_compute_ring_get_wptr,
-                       .set_wptr = &cik_compute_ring_set_wptr,
-               },
-               [R600_RING_TYPE_DMA_INDEX] = {
-                       .ib_execute = &cik_sdma_ring_ib_execute,
-                       .ib_parse = &cik_ib_parse,
-                       .emit_fence = &cik_sdma_fence_ring_emit,
-                       .emit_semaphore = &cik_sdma_semaphore_ring_emit,
-                       .cs_parse = NULL,
-                       .ring_test = &cik_sdma_ring_test,
-                       .ib_test = &cik_sdma_ib_test,
-                       .is_lockup = &cik_sdma_is_lockup,
-                       .vm_flush = &cik_dma_vm_flush,
-                       .get_rptr = &radeon_ring_generic_get_rptr,
-                       .get_wptr = &radeon_ring_generic_get_wptr,
-                       .set_wptr = &radeon_ring_generic_set_wptr,
-               },
-               [CAYMAN_RING_TYPE_DMA1_INDEX] = {
-                       .ib_execute = &cik_sdma_ring_ib_execute,
-                       .ib_parse = &cik_ib_parse,
-                       .emit_fence = &cik_sdma_fence_ring_emit,
-                       .emit_semaphore = &cik_sdma_semaphore_ring_emit,
-                       .cs_parse = NULL,
-                       .ring_test = &cik_sdma_ring_test,
-                       .ib_test = &cik_sdma_ib_test,
-                       .is_lockup = &cik_sdma_is_lockup,
-                       .vm_flush = &cik_dma_vm_flush,
-                       .get_rptr = &radeon_ring_generic_get_rptr,
-                       .get_wptr = &radeon_ring_generic_get_wptr,
-                       .set_wptr = &radeon_ring_generic_set_wptr,
-               },
-               [R600_RING_TYPE_UVD_INDEX] = {
-                       .ib_execute = &r600_uvd_ib_execute,
-                       .emit_fence = &r600_uvd_fence_emit,
-                       .emit_semaphore = &cayman_uvd_semaphore_emit,
-                       .cs_parse = &radeon_uvd_cs_parse,
-                       .ring_test = &r600_uvd_ring_test,
-                       .ib_test = &r600_uvd_ib_test,
-                       .is_lockup = &radeon_ring_test_lockup,
-                       .get_rptr = &radeon_ring_generic_get_rptr,
-                       .get_wptr = &radeon_ring_generic_get_wptr,
-                       .set_wptr = &radeon_ring_generic_set_wptr,
-               }
+               [RADEON_RING_TYPE_GFX_INDEX] = &ci_gfx_ring,
+               [CAYMAN_RING_TYPE_CP1_INDEX] = &ci_cp_ring,
+               [CAYMAN_RING_TYPE_CP2_INDEX] = &ci_cp_ring,
+               [R600_RING_TYPE_DMA_INDEX] = &ci_dma_ring,
+               [CAYMAN_RING_TYPE_DMA1_INDEX] = &ci_dma_ring,
+               [R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring,
        },
        .irq = {
                .set = &cik_irq_set,
@@ -2502,88 +2092,12 @@ static struct radeon_asic kv_asic = {
                .set_page = &cik_vm_set_page,
        },
        .ring = {
-               [RADEON_RING_TYPE_GFX_INDEX] = {
-                       .ib_execute = &cik_ring_ib_execute,
-                       .ib_parse = &cik_ib_parse,
-                       .emit_fence = &cik_fence_gfx_ring_emit,
-                       .emit_semaphore = &cik_semaphore_ring_emit,
-                       .cs_parse = NULL,
-                       .ring_test = &cik_ring_test,
-                       .ib_test = &cik_ib_test,
-                       .is_lockup = &cik_gfx_is_lockup,
-                       .vm_flush = &cik_vm_flush,
-                       .get_rptr = &radeon_ring_generic_get_rptr,
-                       .get_wptr = &radeon_ring_generic_get_wptr,
-                       .set_wptr = &radeon_ring_generic_set_wptr,
-               },
-               [CAYMAN_RING_TYPE_CP1_INDEX] = {
-                       .ib_execute = &cik_ring_ib_execute,
-                       .ib_parse = &cik_ib_parse,
-                       .emit_fence = &cik_fence_compute_ring_emit,
-                       .emit_semaphore = &cik_semaphore_ring_emit,
-                       .cs_parse = NULL,
-                       .ring_test = &cik_ring_test,
-                       .ib_test = &cik_ib_test,
-                       .is_lockup = &cik_gfx_is_lockup,
-                       .vm_flush = &cik_vm_flush,
-                       .get_rptr = &cik_compute_ring_get_rptr,
-                       .get_wptr = &cik_compute_ring_get_wptr,
-                       .set_wptr = &cik_compute_ring_set_wptr,
-               },
-               [CAYMAN_RING_TYPE_CP2_INDEX] = {
-                       .ib_execute = &cik_ring_ib_execute,
-                       .ib_parse = &cik_ib_parse,
-                       .emit_fence = &cik_fence_compute_ring_emit,
-                       .emit_semaphore = &cik_semaphore_ring_emit,
-                       .cs_parse = NULL,
-                       .ring_test = &cik_ring_test,
-                       .ib_test = &cik_ib_test,
-                       .is_lockup = &cik_gfx_is_lockup,
-                       .vm_flush = &cik_vm_flush,
-                       .get_rptr = &cik_compute_ring_get_rptr,
-                       .get_wptr = &cik_compute_ring_get_wptr,
-                       .set_wptr = &cik_compute_ring_set_wptr,
-               },
-               [R600_RING_TYPE_DMA_INDEX] = {
-                       .ib_execute = &cik_sdma_ring_ib_execute,
-                       .ib_parse = &cik_ib_parse,
-                       .emit_fence = &cik_sdma_fence_ring_emit,
-                       .emit_semaphore = &cik_sdma_semaphore_ring_emit,
-                       .cs_parse = NULL,
-                       .ring_test = &cik_sdma_ring_test,
-                       .ib_test = &cik_sdma_ib_test,
-                       .is_lockup = &cik_sdma_is_lockup,
-                       .vm_flush = &cik_dma_vm_flush,
-                       .get_rptr = &radeon_ring_generic_get_rptr,
-                       .get_wptr = &radeon_ring_generic_get_wptr,
-                       .set_wptr = &radeon_ring_generic_set_wptr,
-               },
-               [CAYMAN_RING_TYPE_DMA1_INDEX] = {
-                       .ib_execute = &cik_sdma_ring_ib_execute,
-                       .ib_parse = &cik_ib_parse,
-                       .emit_fence = &cik_sdma_fence_ring_emit,
-                       .emit_semaphore = &cik_sdma_semaphore_ring_emit,
-                       .cs_parse = NULL,
-                       .ring_test = &cik_sdma_ring_test,
-                       .ib_test = &cik_sdma_ib_test,
-                       .is_lockup = &cik_sdma_is_lockup,
-                       .vm_flush = &cik_dma_vm_flush,
-                       .get_rptr = &radeon_ring_generic_get_rptr,
-                       .get_wptr = &radeon_ring_generic_get_wptr,
-                       .set_wptr = &radeon_ring_generic_set_wptr,
-               },
-               [R600_RING_TYPE_UVD_INDEX] = {
-                       .ib_execute = &r600_uvd_ib_execute,
-                       .emit_fence = &r600_uvd_fence_emit,
-                       .emit_semaphore = &cayman_uvd_semaphore_emit,
-                       .cs_parse = &radeon_uvd_cs_parse,
-                       .ring_test = &r600_uvd_ring_test,
-                       .ib_test = &r600_uvd_ib_test,
-                       .is_lockup = &radeon_ring_test_lockup,
-                       .get_rptr = &radeon_ring_generic_get_rptr,
-                       .get_wptr = &radeon_ring_generic_get_wptr,
-                       .set_wptr = &radeon_ring_generic_set_wptr,
-               }
+               [RADEON_RING_TYPE_GFX_INDEX] = &ci_gfx_ring,
+               [CAYMAN_RING_TYPE_CP1_INDEX] = &ci_cp_ring,
+               [CAYMAN_RING_TYPE_CP2_INDEX] = &ci_cp_ring,
+               [R600_RING_TYPE_DMA_INDEX] = &ci_dma_ring,
+               [CAYMAN_RING_TYPE_DMA1_INDEX] = &ci_dma_ring,
+               [R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring,
        },
        .irq = {
                .set = &cik_irq_set,

diff --git a/drivers/gpu/drm/radeon/radeon_cs.c b/drivers/gpu/drm/radeon/radeon_cs.c
index 5384fa42c16e4b458e8fe613fc0e6d77747f6d88..a560844103727dce62d2b8ef88290cd321a28936 100644 (file)
--- a/drivers/gpu/drm/radeon/radeon_cs.c
+++ b/drivers/gpu/drm/radeon/radeon_cs.c
@@ -268,7 +268,7 @@ int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data)
                        return -EINVAL;
 
                /* we only support VM on some SI+ rings */
-               if ((p->rdev->asic->ring[p->ring].cs_parse == NULL) &&
+               if ((p->rdev->asic->ring[p->ring]->cs_parse == NULL) &&
                   ((p->cs_flags & RADEON_CS_USE_VM) == 0)) {
                        DRM_ERROR("Ring %d requires VM!\n", p->ring);
                        return -EINVAL;