{
/* enable interrupts */
if ((data->bpw_len) > PCH_MAX_FIFO_DEPTH) {
- /* set receive threhold to PCH_RX_THOLD */
+ /* set receive threshold to PCH_RX_THOLD */
pch_spi_setclr_reg(data->master, PCH_SPCR,
PCH_RX_THOLD << SPCR_RFIC_FIELD,
~MASK_RFIC_SPCR_BITS);
pch_spi_setclr_reg(data->master, PCH_SPCR,
SPCR_RFIE_BIT | SPCR_FIE_BIT, 0);
} else {
- /* set receive threhold to maximum */
+ /* set receive threshold to maximum */
pch_spi_setclr_reg(data->master, PCH_SPCR,
PCH_RX_THOLD_MAX << SPCR_TFIC_FIELD,
~MASK_TFIC_SPCR_BITS);