/*
- * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright (C) 2011-2012 Freescale Semiconductor, Inc. All Rights Reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
static void usbh2_internal_phy_clock_gate(bool on)
{
if (on) {
+ /* must turn on the 480M clock, otherwise
+ * there will be a 10ms delay before host
+ * controller send out resume signal*/
USB_H2_CTRL |= UCTRL_UTMI_ON_CLOCK;
USB_UH2_HSIC_CTRL |= HSIC_CLK_ON;
} else {
USB_UH2_HSIC_CTRL &= ~HSIC_CLK_ON;
- USB_H2_CTRL &= ~UCTRL_UTMI_ON_CLOCK;
+ /* can't turn off this clock, otherwise
+ * there will be a 10ms delay before host
+ * controller send out resume signal*/
+ /*USB_H2_CTRL &= ~UCTRL_UTMI_ON_CLOCK*/;
}
}
static void _wake_up_enable(struct fsl_usb2_platform_data *pdata, bool enable)
{
pr_debug("host2, %s, enable is %d\n", __func__, enable);
+ /* for HSIC, no disconnect nor connect
+ * we need to disable the WKDS, WKCN */
+ UH2_PORTSC1 &= ~(PORTSC_WKDC | PORTSC_WKCN);
+
if (enable) {
USB_H2_CTRL |= (UCTRL_OWIE);
} else {
mxc_iomux_v3_setup_pad(MX6Q_PAD_RGMII_TX_CTL__USBOH3_H2_STROBE_START);
}
+static void hsic_device_connected(void)
+{
+ pr_debug("%s\n", __func__);
+ if (!(USB_UH2_HSIC_CTRL & HSIC_DEV_CONN))
+ USB_UH2_HSIC_CTRL |= HSIC_DEV_CONN;
+}
+
static struct fsl_usb2_platform_data usbh2_config = {
.name = "Host 2",
.init = fsl_usb_host_init_ext,
.wakeup_handler = h2_wakeup_handler,
.transceiver = "hsic_xcvr",
.hsic_post_ops = hsic_start,
+ .hsic_device_connected = hsic_device_connected,
};
static struct fsl_usb2_wakeup_platform_data usbh2_wakeup_config = {
*/
__raw_writel(BM_ANADIG_USB1_PLL_480_CTRL_EN_USB_CLKS,
anatop_base_addr + HW_ANADIG_USB1_PLL_480_CTRL_SET);
+ /* must change the clkgate delay to 2 or 3 to avoid
+ * 24M OSCI clock not stable issue */
+ __raw_writel(BF_ANADIG_ANA_MISC0_CLKGATE_DELAY(3),
+ anatop_base_addr + HW_ANADIG_ANA_MISC0);
}
/*
- * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright (C) 2011-2012 Freescale Semiconductor, Inc. All Rights Reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
static void usbh3_internal_phy_clock_gate(bool on)
{
if (on) {
+ /* must turn on the 480M clock, otherwise
+ * there will be a 10ms delay before host
+ * controller send out resume signal*/
USB_H3_CTRL |= UCTRL_UTMI_ON_CLOCK;
USB_UH3_HSIC_CTRL |= HSIC_CLK_ON;
} else {
USB_UH3_HSIC_CTRL &= ~HSIC_CLK_ON;
- USB_H3_CTRL &= ~UCTRL_UTMI_ON_CLOCK;
+ /* can't turn off this clock, otherwise
+ * there will be a 10ms delay before host
+ * controller send out resume signal*/
+ /*USB_H3_CTRL &= ~UCTRL_UTMI_ON_CLOCK;*/
}
}
static void _wake_up_enable(struct fsl_usb2_platform_data *pdata, bool enable)
{
pr_debug("host3, %s, enable is %d\n", __func__, enable);
+ /* for HSIC, no disconnect nor connect
+ * we need to disable the WKDS, WKCN */
+ UH3_PORTSC1 &= ~(PORTSC_WKDC | PORTSC_WKCN);
+
if (enable) {
USB_H3_CTRL |= (UCTRL_OWIE);
} else {
mxc_iomux_v3_setup_pad(MX6Q_PAD_RGMII_RXC__USBOH3_H3_STROBE_START);
}
+static void hsic_device_connected(void)
+{
+ pr_debug("%s\n", __func__);
+ if (!(USB_UH3_HSIC_CTRL & HSIC_DEV_CONN))
+ USB_UH3_HSIC_CTRL |= HSIC_DEV_CONN;
+}
+
static struct fsl_usb2_platform_data usbh3_config = {
.name = "Host 3",
.init = fsl_usb_host_init_ext,
.wakeup_handler = usbh3_wakeup_handler,
.transceiver = "hsic_xcvr",
.hsic_post_ops = hsic_start,
+ .hsic_device_connected = hsic_device_connected,
};
static struct fsl_usb2_wakeup_platform_data usbh3_wakeup_config = {
*/
__raw_writel(BM_ANADIG_USB1_PLL_480_CTRL_EN_USB_CLKS,
anatop_base_addr + HW_ANADIG_USB1_PLL_480_CTRL_SET);
+ /* must change the clkgate delay to 2 or 3 to avoid
+ * 24M OSCI clock not stable issue */
+ __raw_writel(BF_ANADIG_ANA_MISC0_CLKGATE_DELAY(3),
+ anatop_base_addr + HW_ANADIG_ANA_MISC0);
}
/*
- * Copyright (C) 2005-2011 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright (C) 2005-2012 Freescale Semiconductor, Inc. All Rights Reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
#define PORTSC_PTW (1 << 28) /* UTMI width */
#define PORTSC_HSIC_MODE (1 << 25) /* Only for HSIC */
#define PORTSC_PHCD (1 << 23) /* Low Power Suspend */
+#define PORTSC_WKDC (1 << 21) /* wakeup on discnt*/
+#define PORTSC_WKCN (1 << 20) /* wakeup on connect*/
#define PORTSC_PORT_POWER (1 << 12) /* port power */
#define PORTSC_LS_MASK (3 << 10) /* Line State mask */
#define PORTSC_LS_SE0 (0 << 10) /* SE0 */
/*
* Freescale USBPHY Register Definitions
*
- * Copyright 2008-2011 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2008-2012 Freescale Semiconductor, Inc. All Rights Reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
/* Host2/3 HSIC Ctrl */
#define CLK_VLD (1 << 31) /* Indicating whether HSIC clock is valid */
+#define HSIC_DEV_CONN (1 << 21) /* set after device connected */
#define HSIC_EN (1 << 12) /* HSIC enable */
#define HSIC_CLK_ON (1 << 11) /* Force HSIC module 480M clock on,
* even when in Host is in suspend mode