sh: default to extended TLB support.

All SH-X2 and SH-X3 parts support an extended TLB mode, which has been
left as experimental since support was originally merged. Now that it's
had some time to stabilize and get some exposure to various platforms,
we can drop it as an option and default enable it across the board.

This is also good future proofing for newer parts that will drop support
for the legacy TLB mode completely.

This will also force 3-level page tables for all newer parts, which is
necessary both for the varying page sizes and larger memories.

Signed-off-by: Paul Mundt <lethal@linux-sh.org>

diff --git a/arch/sh/include/asm/pgalloc.h b/arch/sh/include/asm/pgalloc.h
index f8982f4e0405862bf366a4dcbf51a31311743f91..8c00785c60d5b2517dd83c3b75b7ac50b0d10e1d 100644 (file)
--- a/arch/sh/include/asm/pgalloc.h
+++ b/arch/sh/include/asm/pgalloc.h
@@ -9,7 +9,7 @@
 extern pgd_t *pgd_alloc(struct mm_struct *);
 extern void pgd_free(struct mm_struct *mm, pgd_t *pgd);
 
-#ifdef CONFIG_PGTABLE_LEVELS_3
+#if PAGETABLE_LEVELS > 2
 extern void pud_populate(struct mm_struct *mm, pud_t *pudp, pmd_t *pmd);
 extern pmd_t *pmd_alloc_one(struct mm_struct *mm, unsigned long address);
 extern void pmd_free(struct mm_struct *mm, pmd_t *pmd);

diff --git a/arch/sh/include/asm/pgtable.h b/arch/sh/include/asm/pgtable.h
index 78598ec33d0abbcf3f7b13e06e409b7fbb6158b8..856ece07d31b3d5daa4121f4cf50724d39f8e309 100644 (file)
--- a/arch/sh/include/asm/pgtable.h
+++ b/arch/sh/include/asm/pgtable.h
@@ -12,7 +12,7 @@
 #ifndef __ASM_SH_PGTABLE_H
 #define __ASM_SH_PGTABLE_H
 
-#ifdef CONFIG_PGTABLE_LEVELS_3
+#ifdef CONFIG_X2TLB
 #include <asm/pgtable_pmd.h>
 #else
 #include <asm/pgtable_nopmd.h>

diff --git a/arch/sh/include/asm/pgtable_nopmd.h b/arch/sh/include/asm/pgtable_nopmd.h
index f0b525b3cb4a4b404c42a21a7ddeeb20d09123aa..b8355e4057cfcc3f1d6bfa321d42b9da5322cd05 100644 (file)
--- a/arch/sh/include/asm/pgtable_nopmd.h
+++ b/arch/sh/include/asm/pgtable_nopmd.h
@@ -6,17 +6,18 @@
 /*
  * traditional two-level paging structure
  */
+#define PAGETABLE_LEVELS       2
 
 /* PTE bits */
-#define PTE_MAGNITUDE  2       /* 32-bit PTEs */
+#define PTE_MAGNITUDE          2       /* 32-bit PTEs */
 
-#define PTE_SHIFT      PAGE_SHIFT
-#define PTE_BITS       (PTE_SHIFT - PTE_MAGNITUDE)
+#define PTE_SHIFT              PAGE_SHIFT
+#define PTE_BITS               (PTE_SHIFT - PTE_MAGNITUDE)
 
 /* PGD bits */
-#define PGDIR_SHIFT    (PTE_SHIFT + PTE_BITS)
+#define PGDIR_SHIFT            (PTE_SHIFT + PTE_BITS)
 
-#define PTRS_PER_PGD   (PAGE_SIZE / (1 << PTE_MAGNITUDE))
+#define PTRS_PER_PGD           (PAGE_SIZE / (1 << PTE_MAGNITUDE))
 #define USER_PTRS_PER_PGD      (TASK_SIZE/PGDIR_SIZE)
 
 #endif /* __ASM_SH_PGTABLE_NOPMD_H */

diff --git a/arch/sh/include/asm/pgtable_pmd.h b/arch/sh/include/asm/pgtable_pmd.h
index 42a180e534a839cd4c9950c601a3b80fb489ea78..587b05e1d04f4b8e344e909f2a077abc0cd87c2f 100644 (file)
--- a/arch/sh/include/asm/pgtable_pmd.h
+++ b/arch/sh/include/asm/pgtable_pmd.h
@@ -7,11 +7,12 @@
  * Some cores need a 3-level page table layout, for example when using
  * 64-bit PTEs and 4K pages.
  */
+#define PAGETABLE_LEVELS       3
 
-#define PTE_MAGNITUDE  3       /* 64-bit PTEs on extended mode SH-X2 TLB */
+#define PTE_MAGNITUDE          3       /* 64-bit PTEs on SH-X2 TLB */
 
 /* PGD bits */
-#define PGDIR_SHIFT    30
+#define PGDIR_SHIFT            30
 
 #define PTRS_PER_PGD           4
 #define USER_PTRS_PER_PGD      2

diff --git a/arch/sh/mm/Kconfig b/arch/sh/mm/Kconfig
index 860cd24b4205e7910fe76e0378ab4c66a8e9b09b..7a4ebc8cbaddf8b4df3fcdcefbbd1eeaf9810576 100644 (file)
--- a/arch/sh/mm/Kconfig
+++ b/arch/sh/mm/Kconfig
@@ -100,13 +100,8 @@ config PMB_LEGACY
          and allows systems to support up to 512MiB of system memory.
 
 config X2TLB
-       bool "Enable extended TLB mode"
-       depends on (CPU_SHX2 || CPU_SHX3) && MMU && EXPERIMENTAL
-       help
-         Selecting this option will enable the extended mode of the SH-X2
-         TLB. For legacy SH-X behaviour and interoperability, say N. For
-         all of the fun new features and a willingless to submit bug reports,
-         say Y.
+       def_bool y
+       depends on (CPU_SHX2 || CPU_SHX3) && MMU
 
 config VSYSCALL
        bool "Support vsyscall page"
@@ -174,32 +169,12 @@ config ARCH_MEMORY_PROBE
        def_bool y
        depends on MEMORY_HOTPLUG
 
-choice
-       prompt "Page table layout"
-       default PGTABLE_LEVELS_3 if X2TLB
-       default PGTABLE_LEVELS_2
-
-config PGTABLE_LEVELS_2
-       bool "2 Levels"
-       help
-         This is the default page table layout for all SuperH CPUs.
-
-config PGTABLE_LEVELS_3
-       bool "3 Levels"
-       depends on X2TLB
-       help
-         This enables a 3 level page table structure.
-
-endchoice
-
 choice
        prompt "Kernel page size"
-       default PAGE_SIZE_8KB if X2TLB
        default PAGE_SIZE_4KB
 
 config PAGE_SIZE_4KB
        bool "4kB"
-       depends on !MMU || !X2TLB || PGTABLE_LEVELS_3
        help
          This is the default page size used by all SuperH CPUs.
 

diff --git a/arch/sh/mm/pgtable.c b/arch/sh/mm/pgtable.c
index e1bc5483cc07de9c880568c224606331d29aa4b4..6f21fb1d8726e257abf6ebd46210fc3383a94cdf 100644 (file)
--- a/arch/sh/mm/pgtable.c
+++ b/arch/sh/mm/pgtable.c
@@ -3,8 +3,7 @@
 #define PGALLOC_GFP GFP_KERNEL | __GFP_REPEAT | __GFP_ZERO
 
 static struct kmem_cache *pgd_cachep;
-
-#ifdef CONFIG_PGTABLE_LEVELS_3
+#if PAGETABLE_LEVELS > 2
 static struct kmem_cache *pmd_cachep;
 #endif
 
@@ -22,7 +21,7 @@ void pgtable_cache_init(void)
        pgd_cachep = kmem_cache_create("pgd_cache",
                                       PTRS_PER_PGD * (1<<PTE_MAGNITUDE),
                                       PAGE_SIZE, SLAB_PANIC, pgd_ctor);
-#ifdef CONFIG_PGTABLE_LEVELS_3
+#if PAGETABLE_LEVELS > 2
        pmd_cachep = kmem_cache_create("pmd_cache",
                                       PTRS_PER_PMD * (1<<PTE_MAGNITUDE),
                                       PAGE_SIZE, SLAB_PANIC, NULL);
@@ -39,7 +38,7 @@ void pgd_free(struct mm_struct *mm, pgd_t *pgd)
        kmem_cache_free(pgd_cachep, pgd);
 }
 
-#ifdef CONFIG_PGTABLE_LEVELS_3
+#if PAGETABLE_LEVELS > 2
 void pud_populate(struct mm_struct *mm, pud_t *pud, pmd_t *pmd)
 {
        set_pud(pud, __pud((unsigned long)pmd));
@@ -54,4 +53,4 @@ void pmd_free(struct mm_struct *mm, pmd_t *pmd)
 {
        kmem_cache_free(pmd_cachep, pmd);
 }
-#endif /* CONFIG_PGTABLE_LEVELS_3 */
+#endif /* PAGETABLE_LEVELS > 2 */