#define PHY_HS2LP_MAXTIME (0x40)
#define PHY_STOP_WAIT_TIME (0x20)
#define DSI_CLKMGR_CFG_CLK_DIV (0x107)
+#define DSI_GEN_PLD_DATA_BUF_ENTRY (0x10)
#define MIPI_MUX_CTRL(v) (((v) & 0x3) << 4)
#define IOMUXC_GPR3_OFFSET (0xc)
#define MIPI_LCD_SLEEP_MODE_DELAY (120)
+#define MIPI_DSI_REG_RW_TIMEOUT (20)
+#define MIPI_DSI_PHY_TIMEOUT (10)
static struct mipi_dsi_match_lcd mipi_dsi_lcd_db[] = {
#ifdef CONFIG_FB_MXC_TRULY_WVGA_SYNC_PANEL
u8 data_type, const u32 *buf, int len)
{
u32 val;
- u32 status;
+ u32 status = 0;
int write_len = len;
+ uint32_t timeout = 0;
if (len) {
/* generic long write command */
mipi_dsi_read_register(mipi_dsi,
MIPI_DSI_CMD_PKT_STATUS, &status);
while ((status & DSI_CMD_PKT_STATUS_GEN_PLD_W_FULL) ==
- DSI_CMD_PKT_STATUS_GEN_PLD_W_FULL)
+ DSI_CMD_PKT_STATUS_GEN_PLD_W_FULL) {
+ msleep(1);
+ timeout++;
+ if (timeout == MIPI_DSI_REG_RW_TIMEOUT)
+ return -EIO;
mipi_dsi_read_register(mipi_dsi,
MIPI_DSI_CMD_PKT_STATUS, &status);
+ }
}
/* write the remainder bytes */
if (len > 0) {
- mipi_dsi_read_register(mipi_dsi,
- MIPI_DSI_CMD_PKT_STATUS, &status);
while ((status & DSI_CMD_PKT_STATUS_GEN_PLD_W_FULL) ==
- DSI_CMD_PKT_STATUS_GEN_PLD_W_FULL)
+ DSI_CMD_PKT_STATUS_GEN_PLD_W_FULL) {
+ msleep(1);
+ timeout++;
+ if (timeout == MIPI_DSI_REG_RW_TIMEOUT)
+ return -EIO;
mipi_dsi_read_register(mipi_dsi,
MIPI_DSI_CMD_PKT_STATUS, &status);
-
+ }
mipi_dsi_write_register(mipi_dsi,
MIPI_DSI_GEN_PLD_DATA, *buf);
}
mipi_dsi_read_register(mipi_dsi, MIPI_DSI_CMD_PKT_STATUS, &status);
while ((status & DSI_CMD_PKT_STATUS_GEN_CMD_FULL) ==
- DSI_CMD_PKT_STATUS_GEN_CMD_FULL)
+ DSI_CMD_PKT_STATUS_GEN_CMD_FULL) {
+ msleep(1);
+ timeout++;
+ if (timeout == MIPI_DSI_REG_RW_TIMEOUT)
+ return -EIO;
mipi_dsi_read_register(mipi_dsi, MIPI_DSI_CMD_PKT_STATUS,
&status);
+ }
mipi_dsi_write_register(mipi_dsi, MIPI_DSI_GEN_HDR, val);
mipi_dsi_read_register(mipi_dsi, MIPI_DSI_CMD_PKT_STATUS, &status);
while (!((status & DSI_CMD_PKT_STATUS_GEN_CMD_EMPTY) ==
DSI_CMD_PKT_STATUS_GEN_CMD_EMPTY) ||
!((status & DSI_CMD_PKT_STATUS_GEN_PLD_W_EMPTY) ==
- DSI_CMD_PKT_STATUS_GEN_PLD_W_EMPTY))
+ DSI_CMD_PKT_STATUS_GEN_PLD_W_EMPTY)) {
+ msleep(1);
+ timeout++;
+ if (timeout == MIPI_DSI_REG_RW_TIMEOUT)
+ return -EIO;
mipi_dsi_read_register(mipi_dsi, MIPI_DSI_CMD_PKT_STATUS,
&status);
+ }
return 0;
}
{
u32 val;
int read_len = 0;
+ uint32_t timeout = 0;
if (!len) {
mipi_dbg("%s, len = 0 invalid error!\n", __func__);
val = data_type | ((*buf & DSI_GEN_HDR_DATA_MASK)
<< DSI_GEN_HDR_DATA_SHIFT);
+ memset(buf, 0, len);
mipi_dsi_write_register(mipi_dsi, MIPI_DSI_GEN_HDR, val);
- /* wait for entire response stroed in FIFO */
+ /* wait for cmd to sent out */
mipi_dsi_read_register(mipi_dsi, MIPI_DSI_CMD_PKT_STATUS, &val);
while ((val & DSI_CMD_PKT_STATUS_GEN_RD_CMD_BUSY) !=
- DSI_CMD_PKT_STATUS_GEN_RD_CMD_BUSY)
+ DSI_CMD_PKT_STATUS_GEN_RD_CMD_BUSY) {
+ msleep(1);
+ timeout++;
+ if (timeout == MIPI_DSI_REG_RW_TIMEOUT)
+ return -EIO;
+ mipi_dsi_read_register(mipi_dsi, MIPI_DSI_CMD_PKT_STATUS,
+ &val);
+ }
+ /* wait for entire response stroed in FIFO */
+ while ((val & DSI_CMD_PKT_STATUS_GEN_RD_CMD_BUSY) ==
+ DSI_CMD_PKT_STATUS_GEN_RD_CMD_BUSY) {
+ msleep(1);
+ timeout++;
+ if (timeout == MIPI_DSI_REG_RW_TIMEOUT)
+ return -EIO;
mipi_dsi_read_register(mipi_dsi, MIPI_DSI_CMD_PKT_STATUS,
&val);
+ }
+ mipi_dsi_read_register(mipi_dsi, MIPI_DSI_CMD_PKT_STATUS, &val);
while (!(val & DSI_CMD_PKT_STATUS_GEN_PLD_R_EMPTY)) {
mipi_dsi_read_register(mipi_dsi, MIPI_DSI_GEN_PLD_DATA, buf);
read_len += DSI_GEN_PLD_DATA_BUF_SIZE;
buf++;
mipi_dsi_read_register(mipi_dsi, MIPI_DSI_CMD_PKT_STATUS,
&val);
+ if (read_len == (DSI_GEN_PLD_DATA_BUF_ENTRY *
+ DSI_GEN_PLD_DATA_BUF_SIZE))
+ break;
}
if ((len <= read_len) &&
else {
dev_err(&mipi_dsi->pdev->dev,
"actually read_len:%d != len:%d.\n", read_len, len);
- return -EIO;
+ return -ERANGE;
}
}
u32 cmd, u32 data)
{
u32 val;
+ u32 timeout = 0;
mipi_dsi_write_register(mipi_dsi, MIPI_DSI_PHY_IF_CTRL,
DSI_PHY_IF_CTRL_RESET);
mipi_dsi_write_register(mipi_dsi, MIPI_DSI_PHY_RSTZ, val);
mipi_dsi_read_register(mipi_dsi, MIPI_DSI_PHY_STATUS, &val);
- while ((val & DSI_PHY_STATUS_LOCK) != DSI_PHY_STATUS_LOCK)
+ while ((val & DSI_PHY_STATUS_LOCK) != DSI_PHY_STATUS_LOCK) {
+ msleep(1);
+ timeout++;
+ if (timeout == MIPI_DSI_PHY_TIMEOUT) {
+ dev_err(&mipi_dsi->pdev->dev,
+ "Error: phy lock timeout!\n");
+ break;
+ }
mipi_dsi_read_register(mipi_dsi, MIPI_DSI_PHY_STATUS, &val);
+ }
+ timeout = 0;
while ((val & DSI_PHY_STATUS_STOPSTATE_CLK_LANE) !=
- DSI_PHY_STATUS_STOPSTATE_CLK_LANE)
+ DSI_PHY_STATUS_STOPSTATE_CLK_LANE) {
+ msleep(1);
+ timeout++;
+ if (timeout == MIPI_DSI_PHY_TIMEOUT) {
+ dev_err(&mipi_dsi->pdev->dev,
+ "Error: phy lock lane timeout!\n");
+ break;
+ }
mipi_dsi_read_register(mipi_dsi, MIPI_DSI_PHY_STATUS, &val);
+ }
}
static void mipi_dsi_enable_controller(struct mipi_dsi_info *mipi_dsi,
<< DSI_DPI_CFG_VID_SHIFT;
mipi_dsi_write_register(mipi_dsi, MIPI_DSI_DPI_CFG, val);
- val = DSI_PCKHDL_CFG_EN_EOTP_TX |
- DSI_PCKHDL_CFG_EN_EOTP_RX |
- DSI_PCKHDL_CFG_EN_BTA |
+ val = DSI_PCKHDL_CFG_EN_BTA |
DSI_PCKHDL_CFG_EN_ECC_RX |
DSI_PCKHDL_CFG_EN_CRC_RX;
- val |= ((lcd_config->virtual_ch + 1) &
- DSI_PCKHDL_CFG_GEN_VID_RX_MASK)
- << DSI_PCKHDL_CFG_GEN_VID_RX_SHIFT;
mipi_dsi_write_register(mipi_dsi, MIPI_DSI_PCKHDL_CFG, val);
val = (mode->xres & DSI_VID_PKT_CFG_VID_PKT_SZ_MASK)
mipi_dsi->dphy_pll_config = mipi_dsi_phy_pll_clk_table[--i].config;
dev_dbg(dev, "dphy_pll_config:0x%x.\n", mipi_dsi->dphy_pll_config);
- mipi_dsi_enable_controller(mipi_dsi, true);
return 0;
}
-static int mipi_dsi_fb_event(struct notifier_block *nb,
- unsigned long event, void *data)
+int mipi_dsi_enable(struct mxc_dispdrv_handle *disp)
{
- struct mipi_dsi_info *mipi_dsi =
- container_of(nb, struct mipi_dsi_info, nb);
- struct fb_event *fbevent = data;
- struct fb_info *fbi = fbevent->info;
- char *id_di[] = {
- "DISP4 BG",
- "DISP4 BG - DI1",
- };
- char *id;
int err;
+ struct mipi_dsi_info *mipi_dsi = mxc_dispdrv_getdata(disp);
- id = id_di[mipi_dsi->disp_id];
- *(id + 4) = mipi_dsi->ipu_id ? '4' : '3';
- if (strcmp(id_di[mipi_dsi->disp_id], fbi->fix.id))
- return 0;
-
- switch (event) {
- case FB_EVENT_BLANK:
- if (*((int *)fbevent->data) == FB_BLANK_UNBLANK) {
- if (!mipi_dsi->lcd_inited) {
- err = mipi_dsi->lcd_callback->mipi_lcd_setup(
- mipi_dsi);
- if (err < 0) {
- dev_err(&mipi_dsi->pdev->dev,
- "failed to init mipi lcd.");
- return err;
- }
- mipi_dsi_set_mode(mipi_dsi, false);
- mipi_dsi->dsi_power_on = 1;
- mipi_dsi->lcd_inited = 1;
- }
- mipi_dsi_power_on(mipi_dsi->disp_mipi);
+ if (!mipi_dsi->lcd_inited) {
+ err = clk_enable(mipi_dsi->dphy_clk);
+ if (err)
+ dev_err(&mipi_dsi->pdev->dev,
+ "clk_enable error:%d!\n", err);
+ mipi_dsi_enable_controller(mipi_dsi, true);
+ err = mipi_dsi->lcd_callback->mipi_lcd_setup(
+ mipi_dsi);
+ if (err < 0) {
+ dev_err(&mipi_dsi->pdev->dev,
+ "failed to init mipi lcd.");
+ clk_disable(mipi_dsi->dphy_clk);
+ return err;
}
- break;
-
- default:
- break;
+ mipi_dsi_set_mode(mipi_dsi, false);
+ mipi_dsi->dsi_power_on = 1;
+ mipi_dsi->lcd_inited = 1;
}
+ mipi_dsi_power_on(mipi_dsi->disp_mipi);
return 0;
}
return -EINVAL;
}
- if ((1 != pdata->ipu_id) || (1 != pdata->disp_id))
- dev_warn(dev, "only work bidirection mode on IPU1-DI1\n");
-
mipi_dsi->lcd_panel = kstrdup(pdata->lcd_panel, GFP_KERNEL);
if (!mipi_dsi->lcd_panel)
return -ENOMEM;
err = PTR_ERR(mipi_dsi->dphy_clk);
goto err_clk;
}
- err = clk_enable(mipi_dsi->dphy_clk);
- if (err)
- dev_err(dev, "clk_enable error:%d!\n", err);
dev_dbg(dev, "got resources: regs %p, irq:%d\n",
mipi_dsi->mmio_base, mipi_dsi->irq);
if (pdata->reset)
pdata->reset();
- mipi_dsi->nb.notifier_call = mipi_dsi_fb_event;
- err = fb_register_client(&mipi_dsi->nb);
- if (err < 0) {
- dev_err(dev, "failed to register fb notifier\n");
- goto err_reg_nb;
- }
mipi_dsi->ipu_id = pdata->ipu_id;
mipi_dsi->disp_id = pdata->disp_id;
mipi_dsi->reset = pdata->reset;
err_dsi_lcd:
free_irq(mipi_dsi->irq, mipi_dsi);
err_req_irq:
- fb_unregister_client(&mipi_dsi->nb);
-err_reg_nb:
if (pdata->exit)
pdata->exit(mipi_dsi->pdev);
err_pdata_init:
if (mipi_dsi->io_regulator)
regulator_put(mipi_dsi->io_regulator);
err_ioreg:
- clk_disable(mipi_dsi->dphy_clk);
clk_put(mipi_dsi->dphy_clk);
err_clk:
err_get_irq:
disable_irq(mipi_dsi->irq);
free_irq(mipi_dsi->irq, mipi_dsi);
mipi_dsi_power_off(mipi_dsi->disp_mipi);
- fb_unregister_client(&mipi_dsi->nb);
if (mipi_dsi->bl)
backlight_device_unregister(mipi_dsi->bl);
if (mipi_dsi->analog_regulator)
.name = DISPDRV_MIPI,
.init = mipi_dsi_disp_init,
.deinit = mipi_dsi_disp_deinit,
+ .enable = mipi_dsi_enable,
.disable = mipi_dsi_power_off,
};
#include "mipi_dsi.h"
+#define MIPI_DSI_MAX_RET_PACK_SIZE (0x4)
+
#define HX8369BL_MAX_BRIGHT (255)
#define HX8369BL_DEF_BRIGHT (255)
#define HX8369_CMD_SETEXTC_LEN (0x4)
#define HX8369_CMD_SETEXTC_PARAM_1 (0x6983ff)
+#define HX8369_CMD_GETHXID (0xF4)
+#define HX8369_CMD_GETHXID_LEN (0x4)
+#define HX8369_ID (0x69)
+#define HX8369_ID_MASK (0xFF)
+
#define HX8369_CMD_SETDISP (0xB2)
#define HX8369_CMD_SETDISP_LEN (16)
#define HX8369_CMD_SETDISP_1_HALT (0x00)
#define HX8369_CMD_WRT_CTRL_DISP (0x53)
#define HX8369_CMD_WRT_CTRL_DISP_PARAM_1 (0x24)
+
+#define CHECK_RETCODE(ret) \
+do { \
+ if (ret < 0) { \
+ dev_err(&mipi_dsi->pdev->dev, \
+ "%s ERR: ret:%d, line:%d.\n", \
+ __func__, ret, __LINE__); \
+ return ret; \
+ } \
+} while (0)
+
static int hx8369bl_brightness;
static int mipid_init_backlight(struct mipi_dsi_info *mipi_dsi);
void mipid_hx8369_get_lcd_videomode(struct fb_videomode **mode, int *size,
struct mipi_lcd_config **data)
{
+ if (cpu_is_mx6dl())
+ truly_lcd_modedb[0].pixclock = 37037; /* 27M clock*/
*mode = &truly_lcd_modedb[0];
*size = ARRAY_SIZE(truly_lcd_modedb);
*data = &lcd_config;
u32 buf[DSI_CMD_BUF_MAXSIZE];
int err;
+ dev_dbg(&mipi_dsi->pdev->dev, "MIPI DSI LCD setup.\n");
buf[0] = HX8369_CMD_SETEXTC | (HX8369_CMD_SETEXTC_PARAM_1 << 8);
- mipi_dsi_pkt_write(mipi_dsi, MIPI_DSI_GENERIC_LONG_WRITE,
- buf, HX8369_CMD_SETEXTC_LEN);
+ err = mipi_dsi_pkt_write(mipi_dsi, MIPI_DSI_GENERIC_LONG_WRITE,
+ buf, HX8369_CMD_SETEXTC_LEN);
+ CHECK_RETCODE(err);
+ buf[0] = MIPI_DSI_MAX_RET_PACK_SIZE;
+ err = mipi_dsi_pkt_write(mipi_dsi,
+ MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE,
+ buf, 0);
+ CHECK_RETCODE(err);
+ buf[0] = HX8369_CMD_GETHXID;
+ err = mipi_dsi_pkt_read(mipi_dsi,
+ MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM,
+ buf, HX8369_CMD_GETHXID_LEN);
+ if (!err && ((buf[0] & HX8369_ID_MASK) == HX8369_ID)) {
+ dev_info(&mipi_dsi->pdev->dev,
+ "MIPI DSI LCD ID:0x%x.\n", buf[0]);
+ } else {
+ dev_err(&mipi_dsi->pdev->dev,
+ "mipi_dsi_pkt_read err:%d, data:0x%x.\n",
+ err, buf[0]);
+ dev_info(&mipi_dsi->pdev->dev,
+ "MIPI DSI LCD not detected!\n");
+ return err;
+ }
+
/* set LCD resolution as 480RGBx800, DPI interface,
* display operation mode: RGB data bypass GRAM mode.
*/
(HX8369_CMD_SETDISP_13_FP_PE << 8) |
(HX8369_CMD_SETDISP_14_RTN_PE << 16) |
(HX8369_CMD_SETDISP_15_GON << 24);
- mipi_dsi_pkt_write(mipi_dsi, MIPI_DSI_GENERIC_LONG_WRITE,
+ err = mipi_dsi_pkt_write(mipi_dsi, MIPI_DSI_GENERIC_LONG_WRITE,
buf, HX8369_CMD_SETDISP_LEN);
+ CHECK_RETCODE(err);
+
/* Set display waveform cycle */
buf[0] = HX8369_CMD_SETCYC | (HX8369_CMD_SETCYC_PARAM_1 << 8);
buf[1] = HX8369_CMD_SETCYC_PARAM_2;
- mipi_dsi_pkt_write(mipi_dsi, MIPI_DSI_GENERIC_LONG_WRITE,
+ err = mipi_dsi_pkt_write(mipi_dsi, MIPI_DSI_GENERIC_LONG_WRITE,
buf, HX8369_CMD_SETCYC_LEN);
+ CHECK_RETCODE(err);
/* Set GIP timing output control */
buf[0] = HX8369_CMD_SETGIP | (HX8369_CMD_SETGIP_PARAM_1 << 8);
buf[4] = HX8369_CMD_SETGIP_PARAM_5;
buf[5] = HX8369_CMD_SETGIP_PARAM_6;
buf[6] = HX8369_CMD_SETGIP_PARAM_7;
- mipi_dsi_pkt_write(mipi_dsi, MIPI_DSI_GENERIC_LONG_WRITE, buf,
+ err = mipi_dsi_pkt_write(mipi_dsi, MIPI_DSI_GENERIC_LONG_WRITE, buf,
HX8369_CMD_SETGIP_LEN);
+ CHECK_RETCODE(err);
/* Set power: standby, DC etc. */
buf[0] = HX8369_CMD_SETPOWER | (HX8369_CMD_SETPOWER_PARAM_1 << 8);
buf[2] = HX8369_CMD_SETPOWER_PARAM_3;
buf[3] = HX8369_CMD_SETPOWER_PARAM_4;
buf[4] = HX8369_CMD_SETPOWER_PARAM_5;
- mipi_dsi_pkt_write(mipi_dsi, MIPI_DSI_GENERIC_LONG_WRITE, buf,
+ err = mipi_dsi_pkt_write(mipi_dsi, MIPI_DSI_GENERIC_LONG_WRITE, buf,
HX8369_CMD_SETPOWER_LEN);
+ CHECK_RETCODE(err);
/* Set VCOM voltage. */
buf[0] = HX8369_CMD_SETVCOM | (HX8369_CMD_SETVCOM_PARAM_1 << 8);
- mipi_dsi_pkt_write(mipi_dsi, MIPI_DSI_GENERIC_LONG_WRITE, buf,
+ err = mipi_dsi_pkt_write(mipi_dsi, MIPI_DSI_GENERIC_LONG_WRITE, buf,
HX8369_CMD_SETVCOM_LEN);
+ CHECK_RETCODE(err);
/* Set Panel: BGR/RGB or Inversion. */
buf[0] = HX8369_CMD_SETPANEL | (HX8369_CMD_SETPANEL_PARAM_1 << 8);
- mipi_dsi_pkt_write(mipi_dsi,
+ err = mipi_dsi_pkt_write(mipi_dsi,
MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM, buf, 0);
+ CHECK_RETCODE(err);
/* Set gamma curve related setting */
buf[0] = HX8369_CMD_SETGAMMA | (HX8369_CMD_SETGAMMA_PARAM_1 << 8);
buf[7] = HX8369_CMD_SETGAMMA_PARAM_7;
buf[7] = HX8369_CMD_SETGAMMA_PARAM_8;
buf[8] = HX8369_CMD_SETGAMMA_PARAM_9;
- mipi_dsi_pkt_write(mipi_dsi, MIPI_DSI_GENERIC_LONG_WRITE, buf,
+ err = mipi_dsi_pkt_write(mipi_dsi, MIPI_DSI_GENERIC_LONG_WRITE, buf,
HX8369_CMD_SETGAMMA_LEN);
+ CHECK_RETCODE(err);
/* Set MIPI: DPHYCMD & DSICMD, data lane number */
buf[0] = HX8369_CMD_SETMIPI | (HX8369_CMD_SETMIPI_PARAM_1 << 8);
else
buf[2] |= HX8369_CMD_SETMIPI_TWOLANE;
buf[3] = HX8369_CMD_SETMIPI_PARAM_4;
- mipi_dsi_pkt_write(mipi_dsi, MIPI_DSI_GENERIC_LONG_WRITE, buf,
+ err = mipi_dsi_pkt_write(mipi_dsi, MIPI_DSI_GENERIC_LONG_WRITE, buf,
HX8369_CMD_SETMIPI_LEN);
+ CHECK_RETCODE(err);
/* Set pixel format:24bpp */
buf[0] = HX8369_CMD_SETPIXEL_FMT;
buf[0] |= (HX8369_CMD_SETPIXEL_FMT_24BPP << 8);
break;
}
- mipi_dsi_pkt_write(mipi_dsi, MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM,
+ err = mipi_dsi_pkt_write(mipi_dsi, MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM,
buf, 0);
+ CHECK_RETCODE(err);
/* Set column address: 0~479 */
buf[0] = HX8369_CMD_SETCLUMN_ADDR |
(HX8369_CMD_SETCLUMN_ADDR_PARAM_1 << 8);
buf[1] = HX8369_CMD_SETCLUMN_ADDR_PARAM_2;
- mipi_dsi_pkt_write(mipi_dsi, MIPI_DSI_GENERIC_LONG_WRITE,
+ err = mipi_dsi_pkt_write(mipi_dsi, MIPI_DSI_GENERIC_LONG_WRITE,
buf, HX8369_CMD_SETCLUMN_ADDR_LEN);
+ CHECK_RETCODE(err);
/* Set page address: 0~799 */
buf[0] = HX8369_CMD_SETPAGE_ADDR |
(HX8369_CMD_SETPAGE_ADDR_PARAM_1 << 8);
buf[1] = HX8369_CMD_SETPAGE_ADDR_PARAM_2;
- mipi_dsi_pkt_write(mipi_dsi, MIPI_DSI_GENERIC_LONG_WRITE,
+ err = mipi_dsi_pkt_write(mipi_dsi, MIPI_DSI_GENERIC_LONG_WRITE,
buf, HX8369_CMD_SETPAGE_ADDR_LEN);
+ CHECK_RETCODE(err);
/* Set display brightness related */
buf[0] = HX8369_CMD_WRT_DISP_BRIGHT |
(HX8369_CMD_WRT_DISP_BRIGHT_PARAM_1 << 8);
- mipi_dsi_pkt_write(mipi_dsi, MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM,
+ err = mipi_dsi_pkt_write(mipi_dsi, MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM,
buf, 0);
+ CHECK_RETCODE(err);
buf[0] = HX8369_CMD_WRT_CABC_CTRL |
(HX8369_CMD_WRT_CABC_CTRL_PARAM_1 << 8);
- mipi_dsi_pkt_write(mipi_dsi, MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM,
+ err = mipi_dsi_pkt_write(mipi_dsi, MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM,
buf, 0);
+ CHECK_RETCODE(err);
buf[0] = HX8369_CMD_WRT_CTRL_DISP |
(HX8369_CMD_WRT_CTRL_DISP_PARAM_1 << 8);
- mipi_dsi_pkt_write(mipi_dsi, MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM,
+ err = mipi_dsi_pkt_write(mipi_dsi, MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM,
buf, 0);
+ CHECK_RETCODE(err);
/* exit sleep mode and set display on */
buf[0] = MIPI_DCS_EXIT_SLEEP_MODE;
- mipi_dsi_pkt_write(mipi_dsi, MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM,
+ err = mipi_dsi_pkt_write(mipi_dsi, MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM,
buf, 0);
+ CHECK_RETCODE(err);
/* To allow time for the supply voltages
* and clock circuits to stabilize.
*/
msleep(5);
buf[0] = MIPI_DCS_SET_DISPLAY_ON;
- mipi_dsi_pkt_write(mipi_dsi, MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM,
+ err = mipi_dsi_pkt_write(mipi_dsi, MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM,
buf, 0);
+ CHECK_RETCODE(err);
err = mipid_init_backlight(mipi_dsi);
return err;
projects / karo-tx-linux.git / commitdiff