ARM: sun5i: a10s: Merge common controllers into the common DTSI

Some controllers found in the A10s DTSI actually apply to all of the sun5i
family. Move those into the common DTSI so that all SoCs can benefit from
it.

Acked-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>

diff --git a/arch/arm/boot/dts/sun5i-a10s.dtsi b/arch/arm/boot/dts/sun5i-a10s.dtsi
index 5122d1179e59b436f101e680ede0d18c43956f5b..074485782a4afd20277958229c235973819955fd 100644 (file)
--- a/arch/arm/boot/dts/sun5i-a10s.dtsi
+++ b/arch/arm/boot/dts/sun5i-a10s.dtsi
@@ -70,45 +70,9 @@
                                 <&ccu CLK_DE_BE>, <&ccu CLK_HDMI>;
                        status = "disabled";
                };
-
-               framebuffer@0 {
-                       compatible = "allwinner,simple-framebuffer",
-                                    "simple-framebuffer";
-                       allwinner,pipeline = "de_be0-lcd0";
-                       clocks = <&ccu CLK_AHB_LCD>, <&ccu CLK_AHB_DE_BE>, <&ccu CLK_DE_BE>,
-                                <&ccu CLK_TCON_CH0>, <&ccu CLK_DRAM_DE_BE>;
-                       status = "disabled";
-               };
-
-               framebuffer@1 {
-                       compatible = "allwinner,simple-framebuffer",
-                                    "simple-framebuffer";
-                       allwinner,pipeline = "de_be0-lcd0-tve0";
-                       clocks = <&ccu CLK_AHB_TVE>, <&ccu CLK_AHB_LCD>,
-                                <&ccu CLK_AHB_DE_BE>, <&ccu CLK_DE_BE>,
-                                <&ccu CLK_TCON_CH1>, <&ccu CLK_DRAM_DE_BE>;
-                       status = "disabled";
-               };
        };
 
        soc@01c00000 {
-               emac: ethernet@01c0b000 {
-                       compatible = "allwinner,sun4i-a10-emac";
-                       reg = <0x01c0b000 0x1000>;
-                       interrupts = <55>;
-                       clocks = <&ccu CLK_AHB_EMAC>;
-                       allwinner,sram = <&emac_sram 1>;
-                       status = "disabled";
-               };
-
-               mdio: mdio@01c0b080 {
-                       compatible = "allwinner,sun4i-a10-mdio";
-                       reg = <0x01c0b080 0x14>;
-                       status = "disabled";
-                       #address-cells = <1>;
-                       #size-cells = <0>;
-               };
-
                pwm: pwm@01c20e00 {
                        compatible = "allwinner,sun5i-a10s-pwm";
                        reg = <0x01c20e00 0xc>;
@@ -116,26 +80,6 @@
                        #pwm-cells = <3>;
                        status = "disabled";
                };
-
-               uart0: serial@01c28000 {
-                       compatible = "snps,dw-apb-uart";
-                       reg = <0x01c28000 0x400>;
-                       interrupts = <1>;
-                       reg-shift = <2>;
-                       reg-io-width = <4>;
-                       clocks = <&ccu CLK_APB1_UART0>;
-                       status = "disabled";
-               };
-
-               uart2: serial@01c28800 {
-                       compatible = "snps,dw-apb-uart";
-                       reg = <0x01c28800 0x400>;
-                       interrupts = <3>;
-                       reg-shift = <2>;
-                       reg-io-width = <4>;
-                       clocks = <&ccu CLK_APB1_UART2>;
-                       status = "disabled";
-               };
        };
 };
 
@@ -165,15 +109,6 @@
                function = "emac";
        };
 
-       emac_pins_a: emac0@0 {
-               pins = "PD6", "PD7", "PD10",
-                               "PD11", "PD12", "PD13", "PD14",
-                               "PD15", "PD18", "PD19", "PD20",
-                               "PD21", "PD22", "PD23", "PD24",
-                               "PD25", "PD26", "PD27";
-               function = "emac";
-       };
-
        mmc1_pins_a: mmc1@0 {
                pins = "PG3", "PG4", "PG5",
                                 "PG6", "PG7", "PG8";
@@ -193,9 +128,4 @@
 };
 
 &sram_a {
-       emac_sram: sram-section@8000 {
-               compatible = "allwinner,sun4i-a10-sram-a3-a4";
-               reg = <0x8000 0x4000>;
-               status = "disabled";
-       };
 };

diff --git a/arch/arm/boot/dts/sun5i.dtsi b/arch/arm/boot/dts/sun5i.dtsi
index 4175d7a50a1b246240d5f2c02d6f2dc42a91b07e..a2096bf18ffc26f081ad19a4983e303523261eed 100644 (file)
--- a/arch/arm/boot/dts/sun5i.dtsi
+++ b/arch/arm/boot/dts/sun5i.dtsi
@@ -77,6 +77,16 @@
                                 <&ccu CLK_TCON_CH0>, <&ccu CLK_DRAM_DE_BE>;
                        status = "disabled";
                };
+
+               framebuffer@1 {
+                       compatible = "allwinner,simple-framebuffer",
+                                    "simple-framebuffer";
+                       allwinner,pipeline = "de_be0-lcd0-tve0";
+                       clocks = <&ccu CLK_AHB_TVE>, <&ccu CLK_AHB_LCD>,
+                                <&ccu CLK_AHB_DE_BE>, <&ccu CLK_DE_BE>,
+                                <&ccu CLK_TCON_CH1>, <&ccu CLK_DRAM_DE_BE>;
+                       status = "disabled";
+               };
        };
 
        clocks {
@@ -120,6 +130,12 @@
                                ranges = <0 0x00000000 0xc000>;
                        };
 
+                       emac_sram: sram-section@8000 {
+                               compatible = "allwinner,sun4i-a10-sram-a3-a4";
+                               reg = <0x8000 0x4000>;
+                               status = "disabled";
+                       };
+
                        sram_d: sram@00010000 {
                                compatible = "mmio-sram";
                                reg = <0x00010000 0x1000>;
@@ -171,6 +187,23 @@
                        #size-cells = <0>;
                };
 
+               emac: ethernet@01c0b000 {
+                       compatible = "allwinner,sun4i-a10-emac";
+                       reg = <0x01c0b000 0x1000>;
+                       interrupts = <55>;
+                       clocks = <&ccu CLK_AHB_EMAC>;
+                       allwinner,sram = <&emac_sram 1>;
+                       status = "disabled";
+               };
+
+               mdio: mdio@01c0b080 {
+                       compatible = "allwinner,sun4i-a10-mdio";
+                       reg = <0x01c0b080 0x14>;
+                       status = "disabled";
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+               };
+
                tcon0: lcd-controller@01c0c000 {
                        compatible = "allwinner,sun5i-a13-tcon";
                        reg = <0x01c0c000 0x1000>;
@@ -326,6 +359,15 @@
                        #interrupt-cells = <3>;
                        #gpio-cells = <3>;
 
+                       emac_pins_a: emac0@0 {
+                               pins = "PD6", "PD7", "PD10",
+                                      "PD11", "PD12", "PD13", "PD14",
+                                      "PD15", "PD18", "PD19", "PD20",
+                                      "PD21", "PD22", "PD23", "PD24",
+                                      "PD25", "PD26", "PD27";
+                               function = "emac";
+                       };
+
                        i2c0_pins_a: i2c0@0 {
                                pins = "PB0", "PB1";
                                function = "i2c0";
@@ -472,6 +514,16 @@
                        #thermal-sensor-cells = <0>;
                };
 
+               uart0: serial@01c28000 {
+                       compatible = "snps,dw-apb-uart";
+                       reg = <0x01c28000 0x400>;
+                       interrupts = <1>;
+                       reg-shift = <2>;
+                       reg-io-width = <4>;
+                       clocks = <&ccu CLK_APB1_UART0>;
+                       status = "disabled";
+               };
+
                uart1: serial@01c28400 {
                        compatible = "snps,dw-apb-uart";
                        reg = <0x01c28400 0x400>;
@@ -482,6 +534,16 @@
                        status = "disabled";
                };
 
+               uart2: serial@01c28800 {
+                       compatible = "snps,dw-apb-uart";
+                       reg = <0x01c28800 0x400>;
+                       interrupts = <3>;
+                       reg-shift = <2>;
+                       reg-io-width = <4>;
+                       clocks = <&ccu CLK_APB1_UART2>;
+                       status = "disabled";
+               };
+
                uart3: serial@01c28c00 {
                        compatible = "snps,dw-apb-uart";
                        reg = <0x01c28c00 0x400>;