#define AM33XX_PWMSS1_TBCLKEN_SHIFT 1
#define AM33XX_PWMSS2_TBCLKEN_SHIFT 2
+/* DEV Feature register to identify AM33XX features */
+#define AM33XX_DEV_FEATURE 0x604
+#define AM33XX_SGX_MASK BIT(29)
+
/* CONTROL OMAP STATUS register to identify OMAP3 features */
#define OMAP3_CONTROL_OMAP_STATUS 0x044c
omap3_cpuinfo();
}
+void __init am33xx_check_features(void)
+{
+ u32 status;
+
+ omap_features = OMAP3_HAS_NEON;
+
+ status = omap_ctrl_readl(AM33XX_DEV_FEATURE);
+ if (status & AM33XX_SGX_MASK)
+ omap_features |= OMAP3_HAS_SGX;
+
+ omap3_cpuinfo();
+}
+
void __init omap3xxx_check_revision(void)
{
const char *cpu_rev;
omap2_set_globals_prm(AM33XX_L4_WK_IO_ADDRESS(AM33XX_PRCM_BASE));
omap2_set_globals_cm(AM33XX_L4_WK_IO_ADDRESS(AM33XX_PRCM_BASE), NULL);
omap3xxx_check_revision();
- ti81xx_check_features();
+ am33xx_check_features();
am33xx_voltagedomains_init();
am33xx_powerdomains_init();
am33xx_clockdomains_init();
void omap5xxx_check_revision(void);
void omap3xxx_check_features(void);
void ti81xx_check_features(void);
+void am33xx_check_features(void);
void omap4xxx_check_features(void);
/*