ARM: dts: imx6: add anatop phandle for usbphy

Add anatop phandle for usbphy

Signed-off-by: Peter Chen <peter.chen@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
[shawn.guo: cherry-pick commit 76a388550675 from upstream]

diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi
index 9ce87691e9e49bfd757cda761e098597d0768c24..148218366af68aa255604478ad23400a36842f3f 100644 (file)
--- a/arch/arm/boot/dts/imx6qdl.dtsi
+++ b/arch/arm/boot/dts/imx6qdl.dtsi
@@ -573,6 +573,7 @@
                                reg = <0x020c9000 0x1000>;
                                interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>;
                                clocks = <&clks 182>;
+                               fsl,anatop = <&anatop>;
                        };
 
                        usbphy2: usbphy@020ca000 {
@@ -580,6 +581,7 @@
                                reg = <0x020ca000 0x1000>;
                                interrupts = <0 45 IRQ_TYPE_LEVEL_HIGH>;
                                clocks = <&clks 183>;
+                               fsl,anatop = <&anatop>;
                        };
 
                        snvs@020cc000 {

diff --git a/arch/arm/boot/dts/imx6sl.dtsi b/arch/arm/boot/dts/imx6sl.dtsi
index 07bee5616c9ec9cf87238ca5666b482749d5f9bc..a6b7b1979ae340af952711a02cba7a8c15b4323e 100644 (file)
--- a/arch/arm/boot/dts/imx6sl.dtsi
+++ b/arch/arm/boot/dts/imx6sl.dtsi
@@ -525,6 +525,7 @@
                                reg = <0x020c9000 0x1000>;
                                interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>;
                                clocks = <&clks IMX6SL_CLK_USBPHY1>;
+                               fsl,anatop = <&anatop>;
                        };
 
                        usbphy2: usbphy@020ca000 {
@@ -532,6 +533,7 @@
                                reg = <0x020ca000 0x1000>;
                                interrupts = <0 45 IRQ_TYPE_LEVEL_HIGH>;
                                clocks = <&clks IMX6SL_CLK_USBPHY2>;
+                               fsl,anatop = <&anatop>;
                        };
 
                        snvs@020cc000 {