static struct resource mipidsi0_resources[] = {
[0] = {
.start = 0xffc60000,
- .end = 0xffc68fff,
+ .end = 0xffc63073,
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ .start = 0xffc68000,
+ .end = 0xffc680ef,
.flags = IORESOURCE_MEM,
},
};
},
};
+static long ap4evb_clk_optimize(unsigned long target, unsigned long *best_freq,
+ unsigned long *parent_freq);
+
+
static struct sh_mobile_hdmi_info hdmi_info = {
.lcd_chan = &sh_mobile_lcdc1_info.ch[0],
.lcd_dev = &lcdc1_device.dev,
.flags = HDMI_SND_SRC_SPDIF,
+ .clk_optimize_parent = ap4evb_clk_optimize,
};
static struct resource hdmi_resources[] = {
},
};
+static long ap4evb_clk_optimize(unsigned long target, unsigned long *best_freq,
+ unsigned long *parent_freq)
+{
+ struct clk *hdmi_ick = clk_get(&hdmi_device.dev, "ick");
+ long error;
+
+ if (IS_ERR(hdmi_ick)) {
+ int ret = PTR_ERR(hdmi_ick);
+ pr_err("Cannot get HDMI ICK: %d\n", ret);
+ return ret;
+ }
+
+ error = clk_round_parent(hdmi_ick, target, best_freq, parent_freq, 1, 64);
+
+ clk_put(hdmi_ick);
+
+ return error;
+}
+
static struct gpio_led ap4evb_leds[] = {
{
.name = "led4",
depends on FB
default n
+config FB_WMT_GE_ROPS
+ tristate
+ depends on FB
+ default n
+ ---help---
+ Include functions for accelerated rectangle filling and area
+ copying using WonderMedia Graphics Engine operations.
+
config FB_DEFERRED_IO
bool
depends on FB
To compile this driver as a module, choose M here: the
module will be called bfin-lq035q1-fb.
+config FB_BF537_LQ035
+ tristate "SHARP LQ035 TFT LCD (BF537 STAMP)"
+ depends on FB && (BF534 || BF536 || BF537) && I2C_BLACKFIN_TWI
+ select FB_CFB_FILLRECT
+ select FB_CFB_COPYAREA
+ select FB_CFB_IMAGEBLIT
+ select BFIN_GPTIMERS
+ help
+ This is the framebuffer device for a SHARP LQ035Q7DB03 TFT LCD
+ attached to a BF537.
+
+ To compile this driver as a module, choose M here: the
+ module will be called bf537-lq035.
+
+config FB_BFIN_7393
+ tristate "Blackfin ADV7393 Video encoder"
+ depends on FB && BLACKFIN
+ select I2C
+ select FB_CFB_FILLRECT
+ select FB_CFB_COPYAREA
+ select FB_CFB_IMAGEBLIT
+ help
+ This is the framebuffer device for a ADV7393 video encoder
+ attached to a Blackfin on the PPI port.
+ If your Blackfin board has a ADV7393 select Y.
+
+ To compile this driver as a module, choose M here: the
+ module will be called bfin_adv7393fb.
+
+choice
+ prompt "Video mode support"
+ depends on FB_BFIN_7393
+ default NTSC
+
+config NTSC
+ bool 'NTSC 720x480'
+
+config PAL
+ bool 'PAL 720x576'
+
+config NTSC_640x480
+ bool 'NTSC 640x480 (Experimental)'
+
+config PAL_640x480
+ bool 'PAL 640x480 (Experimental)'
+
+config NTSC_YCBCR
+ bool 'NTSC 720x480 YCbCR input'
+
+config PAL_YCBCR
+ bool 'PAL 720x576 YCbCR input'
+
+endchoice
+
+choice
+ prompt "Size of ADV7393 frame buffer memory Single/Double Size"
+ depends on (FB_BFIN_7393)
+ default ADV7393_1XMEM
+
+config ADV7393_1XMEM
+ bool 'Single'
+
+config ADV7393_2XMEM
+ bool 'Double'
+endchoice
+
config FB_STI
tristate "HP STI frame buffer device support"
depends on FB && PARISC
various panels and CRTs by passing in kernel cmd line option
au1200fb:panel=<name>.
+config FB_VT8500
+ bool "VT8500 LCD Driver"
+ depends on (FB = y) && ARM && ARCH_VT8500 && VTWM_VERSION_VT8500
+ select FB_WMT_GE_ROPS
+ select FB_SYS_IMAGEBLIT
+ help
+ This is the framebuffer driver for VIA VT8500 integrated LCD
+ controller.
+
+config FB_WM8505
+ bool "WM8505 frame buffer support"
+ depends on (FB = y) && ARM && ARCH_VT8500 && VTWM_VERSION_WM8505
+ select FB_WMT_GE_ROPS
+ select FB_SYS_IMAGEBLIT
+ help
+ This is the framebuffer driver for WonderMedia WM8505
+ integrated LCD controller.
+
source "drivers/video/geode/Kconfig"
config FB_HIT
obj-$(CONFIG_FB_MACMODES) += macmodes.o
obj-$(CONFIG_FB_DDC) += fb_ddc.o
obj-$(CONFIG_FB_DEFERRED_IO) += fb_defio.o
+obj-$(CONFIG_FB_WMT_GE_ROPS) += wmt_ge_rops.o
# Hardware specific drivers go first
obj-$(CONFIG_FB_AMIGA) += amifb.o c2p_planar.o
obj-$(CONFIG_FB_TMIO) += tmiofb.o
obj-$(CONFIG_FB_AU1100) += au1100fb.o
obj-$(CONFIG_FB_AU1200) += au1200fb.o
+obj-$(CONFIG_FB_VT8500) += vt8500lcdfb.o
+obj-$(CONFIG_FB_WM8505) += wm8505fb.o
obj-$(CONFIG_FB_PMAG_AA) += pmag-aa-fb.o
obj-$(CONFIG_FB_PMAG_BA) += pmag-ba-fb.o
obj-$(CONFIG_FB_PMAGB_B) += pmagb-b-fb.o
obj-$(CONFIG_FB_EFI) += efifb.o
obj-$(CONFIG_FB_VGA16) += vga16fb.o
obj-$(CONFIG_FB_OF) += offb.o
+obj-$(CONFIG_FB_BF537_LQ035) += bf537-lq035.o
obj-$(CONFIG_FB_BF54X_LQ043) += bf54x-lq043fb.o
obj-$(CONFIG_FB_BFIN_LQ035Q1) += bfin-lq035q1-fb.o
obj-$(CONFIG_FB_BFIN_T350MCQB) += bfin-t350mcqb-fb.o
+obj-$(CONFIG_FB_BFIN_7393) += bfin_adv7393fb.o
obj-$(CONFIG_FB_MX3) += mx3fb.o
obj-$(CONFIG_FB_DA8XX) += da8xx-fb.o
--- /dev/null
+/*
+ * Analog Devices Blackfin(BF537 STAMP) + SHARP TFT LCD.
+ * http://docs.blackfin.uclinux.org/doku.php?id=hw:cards:tft-lcd
+ *
+ * Copyright 2006-2010 Analog Devices Inc.
+ * Licensed under the GPL-2.
+ */
+
+#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/errno.h>
+#include <linux/string.h>
+#include <linux/mm.h>
+#include <linux/delay.h>
+#include <linux/fb.h>
+#include <linux/ioport.h>
+#include <linux/init.h>
+#include <linux/types.h>
+#include <linux/gpio.h>
+#include <linux/interrupt.h>
+#include <linux/sched.h>
+#include <linux/timer.h>
+#include <linux/device.h>
+#include <linux/backlight.h>
+#include <linux/lcd.h>
+#include <linux/i2c.h>
+#include <linux/spinlock.h>
+#include <linux/dma-mapping.h>
+#include <linux/slab.h>
+#include <linux/platform_device.h>
+
+#include <asm/blackfin.h>
+#include <asm/irq.h>
+#include <asm/dpmc.h>
+#include <asm/dma.h>
+#include <asm/portmux.h>
+
+#define NO_BL 1
+
+#define MAX_BRIGHENESS 95
+#define MIN_BRIGHENESS 5
+#define NBR_PALETTE 256
+
+static const unsigned short ppi_pins[] = {
+ P_PPI0_CLK, P_PPI0_D0, P_PPI0_D1, P_PPI0_D2, P_PPI0_D3,
+ P_PPI0_D4, P_PPI0_D5, P_PPI0_D6, P_PPI0_D7,
+ P_PPI0_D8, P_PPI0_D9, P_PPI0_D10, P_PPI0_D11,
+ P_PPI0_D12, P_PPI0_D13, P_PPI0_D14, P_PPI0_D15, 0
+};
+
+static unsigned char *fb_buffer; /* RGB Buffer */
+static unsigned long *dma_desc_table;
+static int t_conf_done, lq035_open_cnt;
+static DEFINE_SPINLOCK(bfin_lq035_lock);
+
+static int landscape;
+module_param(landscape, int, 0);
+MODULE_PARM_DESC(landscape,
+ "LANDSCAPE use 320x240 instead of Native 240x320 Resolution");
+
+static int bgr;
+module_param(bgr, int, 0);
+MODULE_PARM_DESC(bgr,
+ "BGR use 16-bit BGR-565 instead of RGB-565");
+
+static int nocursor = 1;
+module_param(nocursor, int, 0644);
+MODULE_PARM_DESC(nocursor, "cursor enable/disable");
+
+static unsigned long current_brightness; /* backlight */
+
+/* AD5280 vcomm */
+static unsigned char vcomm_value = 150;
+static struct i2c_client *ad5280_client;
+
+static void set_vcomm(void)
+{
+ int nr;
+
+ if (!ad5280_client)
+ return;
+
+ nr = i2c_smbus_write_byte_data(ad5280_client, 0x00, vcomm_value);
+ if (nr)
+ pr_err("i2c_smbus_write_byte_data fail: %d\n", nr);
+}
+
+static int __devinit ad5280_probe(struct i2c_client *client,
+ const struct i2c_device_id *id)
+{
+ int ret;
+ if (!i2c_check_functionality(client->adapter,
+ I2C_FUNC_SMBUS_BYTE_DATA)) {
+ dev_err(&client->dev, "SMBUS Byte Data not Supported\n");
+ return -EIO;
+ }
+
+ ret = i2c_smbus_write_byte_data(client, 0x00, vcomm_value);
+ if (ret) {
+ dev_err(&client->dev, "write fail: %d\n", ret);
+ return ret;
+ }
+
+ ad5280_client = client;
+
+ return 0;
+}
+
+static int __devexit ad5280_remove(struct i2c_client *client)
+{
+ ad5280_client = NULL;
+ return 0;
+}
+
+static const struct i2c_device_id ad5280_id[] = {
+ {"bf537-lq035-ad5280", 0},
+ {}
+};
+
+MODULE_DEVICE_TABLE(i2c, ad5280_id);
+
+static struct i2c_driver ad5280_driver = {
+ .driver = {
+ .name = "bf537-lq035-ad5280",
+ },
+ .probe = ad5280_probe,
+ .remove = __devexit_p(ad5280_remove),
+ .id_table = ad5280_id,
+};
+
+#ifdef CONFIG_PNAV10
+#define MOD GPIO_PH13
+
+#define bfin_write_TIMER_LP_CONFIG bfin_write_TIMER0_CONFIG
+#define bfin_write_TIMER_LP_WIDTH bfin_write_TIMER0_WIDTH
+#define bfin_write_TIMER_LP_PERIOD bfin_write_TIMER0_PERIOD
+#define bfin_read_TIMER_LP_COUNTER bfin_read_TIMER0_COUNTER
+#define TIMDIS_LP TIMDIS0
+#define TIMEN_LP TIMEN0
+
+#define bfin_write_TIMER_SPS_CONFIG bfin_write_TIMER1_CONFIG
+#define bfin_write_TIMER_SPS_WIDTH bfin_write_TIMER1_WIDTH
+#define bfin_write_TIMER_SPS_PERIOD bfin_write_TIMER1_PERIOD
+#define TIMDIS_SPS TIMDIS1
+#define TIMEN_SPS TIMEN1
+
+#define bfin_write_TIMER_SP_CONFIG bfin_write_TIMER5_CONFIG
+#define bfin_write_TIMER_SP_WIDTH bfin_write_TIMER5_WIDTH
+#define bfin_write_TIMER_SP_PERIOD bfin_write_TIMER5_PERIOD
+#define TIMDIS_SP TIMDIS5
+#define TIMEN_SP TIMEN5
+
+#define bfin_write_TIMER_PS_CLS_CONFIG bfin_write_TIMER2_CONFIG
+#define bfin_write_TIMER_PS_CLS_WIDTH bfin_write_TIMER2_WIDTH
+#define bfin_write_TIMER_PS_CLS_PERIOD bfin_write_TIMER2_PERIOD
+#define TIMDIS_PS_CLS TIMDIS2
+#define TIMEN_PS_CLS TIMEN2
+
+#define bfin_write_TIMER_REV_CONFIG bfin_write_TIMER3_CONFIG
+#define bfin_write_TIMER_REV_WIDTH bfin_write_TIMER3_WIDTH
+#define bfin_write_TIMER_REV_PERIOD bfin_write_TIMER3_PERIOD
+#define TIMDIS_REV TIMDIS3
+#define TIMEN_REV TIMEN3
+#define bfin_read_TIMER_REV_COUNTER bfin_read_TIMER3_COUNTER
+
+#define FREQ_PPI_CLK (5*1024*1024) /* PPI_CLK 5MHz */
+
+#define TIMERS {P_TMR0, P_TMR1, P_TMR2, P_TMR3, P_TMR5, 0}
+
+#else
+
+#define UD GPIO_PF13 /* Up / Down */
+#define MOD GPIO_PF10
+#define LBR GPIO_PF14 /* Left Right */
+
+#define bfin_write_TIMER_LP_CONFIG bfin_write_TIMER6_CONFIG
+#define bfin_write_TIMER_LP_WIDTH bfin_write_TIMER6_WIDTH
+#define bfin_write_TIMER_LP_PERIOD bfin_write_TIMER6_PERIOD
+#define bfin_read_TIMER_LP_COUNTER bfin_read_TIMER6_COUNTER
+#define TIMDIS_LP TIMDIS6
+#define TIMEN_LP TIMEN6
+
+#define bfin_write_TIMER_SPS_CONFIG bfin_write_TIMER1_CONFIG
+#define bfin_write_TIMER_SPS_WIDTH bfin_write_TIMER1_WIDTH
+#define bfin_write_TIMER_SPS_PERIOD bfin_write_TIMER1_PERIOD
+#define TIMDIS_SPS TIMDIS1
+#define TIMEN_SPS TIMEN1
+
+#define bfin_write_TIMER_SP_CONFIG bfin_write_TIMER0_CONFIG
+#define bfin_write_TIMER_SP_WIDTH bfin_write_TIMER0_WIDTH
+#define bfin_write_TIMER_SP_PERIOD bfin_write_TIMER0_PERIOD
+#define TIMDIS_SP TIMDIS0
+#define TIMEN_SP TIMEN0
+
+#define bfin_write_TIMER_PS_CLS_CONFIG bfin_write_TIMER7_CONFIG
+#define bfin_write_TIMER_PS_CLS_WIDTH bfin_write_TIMER7_WIDTH
+#define bfin_write_TIMER_PS_CLS_PERIOD bfin_write_TIMER7_PERIOD
+#define TIMDIS_PS_CLS TIMDIS7
+#define TIMEN_PS_CLS TIMEN7
+
+#define bfin_write_TIMER_REV_CONFIG bfin_write_TIMER5_CONFIG
+#define bfin_write_TIMER_REV_WIDTH bfin_write_TIMER5_WIDTH
+#define bfin_write_TIMER_REV_PERIOD bfin_write_TIMER5_PERIOD
+#define TIMDIS_REV TIMDIS5
+#define TIMEN_REV TIMEN5
+#define bfin_read_TIMER_REV_COUNTER bfin_read_TIMER5_COUNTER
+
+#define FREQ_PPI_CLK (6*1000*1000) /* PPI_CLK 6MHz */
+#define TIMERS {P_TMR0, P_TMR1, P_TMR5, P_TMR6, P_TMR7, 0}
+
+#endif
+
+#define LCD_X_RES 240 /* Horizontal Resolution */
+#define LCD_Y_RES 320 /* Vertical Resolution */
+
+#define LCD_BBP 16 /* Bit Per Pixel */
+
+/* the LCD and the DMA start counting differently;
+ * since one starts at 0 and the other starts at 1,
+ * we have a difference of 1 between START_LINES
+ * and U_LINES.
+ */
+#define START_LINES 8 /* lines for field flyback or field blanking signal */
+#define U_LINES 9 /* number of undisplayed blanking lines */
+
+#define FRAMES_PER_SEC (60)
+
+#define DCLKS_PER_FRAME (FREQ_PPI_CLK/FRAMES_PER_SEC)
+#define DCLKS_PER_LINE (DCLKS_PER_FRAME/(LCD_Y_RES+U_LINES))
+
+#define PPI_CONFIG_VALUE (PORT_DIR|XFR_TYPE|DLEN_16|POLS)
+#define PPI_DELAY_VALUE (0)
+#define TIMER_CONFIG (PWM_OUT|PERIOD_CNT|TIN_SEL|CLK_SEL)
+
+#define ACTIVE_VIDEO_MEM_OFFSET (LCD_X_RES*START_LINES*(LCD_BBP/8))
+#define ACTIVE_VIDEO_MEM_SIZE (LCD_Y_RES*LCD_X_RES*(LCD_BBP/8))
+#define TOTAL_VIDEO_MEM_SIZE ((LCD_Y_RES+U_LINES)*LCD_X_RES*(LCD_BBP/8))
+#define TOTAL_DMA_DESC_SIZE (2 * sizeof(u32) * (LCD_Y_RES + U_LINES))
+
+static void start_timers(void) /* CHECK with HW */
+{
+ unsigned long flags;
+
+ local_irq_save(flags);
+
+ bfin_write_TIMER_ENABLE(TIMEN_REV);
+ SSYNC();
+
+ while (bfin_read_TIMER_REV_COUNTER() <= 11)
+ continue;
+ bfin_write_TIMER_ENABLE(TIMEN_LP);
+ SSYNC();
+
+ while (bfin_read_TIMER_LP_COUNTER() < 3)
+ continue;
+ bfin_write_TIMER_ENABLE(TIMEN_SP|TIMEN_SPS|TIMEN_PS_CLS);
+ SSYNC();
+ t_conf_done = 1;
+ local_irq_restore(flags);
+}
+
+static void config_timers(void)
+{
+ /* Stop timers */
+ bfin_write_TIMER_DISABLE(TIMDIS_SP|TIMDIS_SPS|TIMDIS_REV|
+ TIMDIS_LP|TIMDIS_PS_CLS);
+ SSYNC();
+
+ /* LP, timer 6 */
+ bfin_write_TIMER_LP_CONFIG(TIMER_CONFIG|PULSE_HI);
+ bfin_write_TIMER_LP_WIDTH(1);
+
+ bfin_write_TIMER_LP_PERIOD(DCLKS_PER_LINE);
+ SSYNC();
+
+ /* SPS, timer 1 */
+ bfin_write_TIMER_SPS_CONFIG(TIMER_CONFIG|PULSE_HI);
+ bfin_write_TIMER_SPS_WIDTH(DCLKS_PER_LINE*2);
+ bfin_write_TIMER_SPS_PERIOD((DCLKS_PER_LINE * (LCD_Y_RES+U_LINES)));
+ SSYNC();
+
+ /* SP, timer 0 */
+ bfin_write_TIMER_SP_CONFIG(TIMER_CONFIG|PULSE_HI);
+ bfin_write_TIMER_SP_WIDTH(1);
+ bfin_write_TIMER_SP_PERIOD(DCLKS_PER_LINE);
+ SSYNC();
+
+ /* PS & CLS, timer 7 */
+ bfin_write_TIMER_PS_CLS_CONFIG(TIMER_CONFIG);
+ bfin_write_TIMER_PS_CLS_WIDTH(LCD_X_RES + START_LINES);
+ bfin_write_TIMER_PS_CLS_PERIOD(DCLKS_PER_LINE);
+
+ SSYNC();
+
+#ifdef NO_BL
+ /* REV, timer 5 */
+ bfin_write_TIMER_REV_CONFIG(TIMER_CONFIG|PULSE_HI);
+
+ bfin_write_TIMER_REV_WIDTH(DCLKS_PER_LINE);
+ bfin_write_TIMER_REV_PERIOD(DCLKS_PER_LINE*2);
+
+ SSYNC();
+#endif
+}
+
+static void config_ppi(void)
+{
+ bfin_write_PPI_DELAY(PPI_DELAY_VALUE);
+ bfin_write_PPI_COUNT(LCD_X_RES-1);
+ /* 0x10 -> PORT_CFG -> 2 or 3 frame syncs */
+ bfin_write_PPI_CONTROL((PPI_CONFIG_VALUE|0x10) & (~POLS));
+}
+
+static int config_dma(void)
+{
+ u32 i;
+
+ if (landscape) {
+
+ for (i = 0; i < U_LINES; ++i) {
+ /* blanking lines point to first line of fb_buffer */
+ dma_desc_table[2*i] = (unsigned long)&dma_desc_table[2*i+2];
+ dma_desc_table[2*i+1] = (unsigned long)fb_buffer;
+ }
+
+ for (i = U_LINES; i < U_LINES + LCD_Y_RES; ++i) {
+ /* visible lines */
+ dma_desc_table[2*i] = (unsigned long)&dma_desc_table[2*i+2];
+ dma_desc_table[2*i+1] = (unsigned long)fb_buffer +
+ (LCD_Y_RES+U_LINES-1-i)*2;
+ }
+
+ /* last descriptor points to first */
+ dma_desc_table[2*(LCD_Y_RES+U_LINES-1)] = (unsigned long)&dma_desc_table[0];
+
+ set_dma_x_count(CH_PPI, LCD_X_RES);
+ set_dma_x_modify(CH_PPI, LCD_Y_RES * (LCD_BBP / 8));
+ set_dma_y_count(CH_PPI, 0);
+ set_dma_y_modify(CH_PPI, 0);
+ set_dma_next_desc_addr(CH_PPI, (void *)dma_desc_table[0]);
+ set_dma_config(CH_PPI, DMAFLOW_LARGE | NDSIZE_4 | WDSIZE_16);
+
+ } else {
+
+ set_dma_config(CH_PPI, set_bfin_dma_config(DIR_READ,
+ DMA_FLOW_AUTO,
+ INTR_DISABLE,
+ DIMENSION_2D,
+ DATA_SIZE_16,
+ DMA_NOSYNC_KEEP_DMA_BUF));
+ set_dma_x_count(CH_PPI, LCD_X_RES);
+ set_dma_x_modify(CH_PPI, LCD_BBP / 8);
+ set_dma_y_count(CH_PPI, LCD_Y_RES+U_LINES);
+ set_dma_y_modify(CH_PPI, LCD_BBP / 8);
+ set_dma_start_addr(CH_PPI, (unsigned long) fb_buffer);
+ }
+
+ return 0;
+}
+
+static int __devinit request_ports(void)
+{
+ u16 tmr_req[] = TIMERS;
+
+ /*
+ UD: PF13
+ MOD: PF10
+ LBR: PF14
+ PPI_CLK: PF15
+ */
+
+ if (peripheral_request_list(ppi_pins, KBUILD_MODNAME)) {
+ pr_err("requesting PPI peripheral failed\n");
+ return -EBUSY;
+ }
+
+ if (peripheral_request_list(tmr_req, KBUILD_MODNAME)) {
+ peripheral_free_list(ppi_pins);
+ pr_err("requesting timer peripheral failed\n");
+ return -EBUSY;
+ }
+
+#if (defined(UD) && defined(LBR))
+ if (gpio_request(UD, KBUILD_MODNAME)) {
+ pr_err("requesting GPIO %d failed\n", UD);
+ return -EBUSY;
+ }
+
+ if (gpio_request(LBR, KBUILD_MODNAME)) {
+ pr_err("requesting GPIO %d failed\n", LBR);
+ gpio_free(UD);
+ return -EBUSY;
+ }
+
+ gpio_direction_output(UD, 0);
+ gpio_direction_output(LBR, 1);
+
+#endif
+
+ if (gpio_request(MOD, KBUILD_MODNAME)) {
+ pr_err("requesting GPIO %d failed\n", MOD);
+#if (defined(UD) && defined(LBR))
+ gpio_free(LBR);
+ gpio_free(UD);
+#endif
+ return -EBUSY;
+ }
+
+ gpio_direction_output(MOD, 1);
+
+ SSYNC();
+ return 0;
+}
+
+static void free_ports(void)
+{
+ u16 tmr_req[] = TIMERS;
+
+ peripheral_free_list(ppi_pins);
+ peripheral_free_list(tmr_req);
+
+#if defined(UD) && defined(LBR)
+ gpio_free(LBR);
+ gpio_free(UD);
+#endif
+ gpio_free(MOD);
+}
+
+static struct fb_info bfin_lq035_fb;
+
+static struct fb_var_screeninfo bfin_lq035_fb_defined = {
+ .bits_per_pixel = LCD_BBP,
+ .activate = FB_ACTIVATE_TEST,
+ .xres = LCD_X_RES, /*default portrait mode RGB*/
+ .yres = LCD_Y_RES,
+ .xres_virtual = LCD_X_RES,
+ .yres_virtual = LCD_Y_RES,
+ .height = -1,
+ .width = -1,
+ .left_margin = 0,
+ .right_margin = 0,
+ .upper_margin = 0,
+ .lower_margin = 0,
+ .red = {11, 5, 0},
+ .green = {5, 6, 0},
+ .blue = {0, 5, 0},
+ .transp = {0, 0, 0},
+};
+
+static struct fb_fix_screeninfo bfin_lq035_fb_fix __devinitdata = {
+ .id = KBUILD_MODNAME,
+ .smem_len = ACTIVE_VIDEO_MEM_SIZE,
+ .type = FB_TYPE_PACKED_PIXELS,
+ .visual = FB_VISUAL_TRUECOLOR,
+ .xpanstep = 0,
+ .ypanstep = 0,
+ .line_length = LCD_X_RES*(LCD_BBP/8),
+ .accel = FB_ACCEL_NONE,
+};
+
+
+static int bfin_lq035_fb_open(struct fb_info *info, int user)
+{
+ unsigned long flags;
+
+ spin_lock_irqsave(&bfin_lq035_lock, flags);
+ lq035_open_cnt++;
+ spin_unlock_irqrestore(&bfin_lq035_lock, flags);
+
+ if (lq035_open_cnt <= 1) {
+ bfin_write_PPI_CONTROL(0);
+ SSYNC();
+
+ set_vcomm();
+ config_dma();
+ config_ppi();
+
+ /* start dma */
+ enable_dma(CH_PPI);
+ SSYNC();
+ bfin_write_PPI_CONTROL(bfin_read_PPI_CONTROL() | PORT_EN);
+ SSYNC();
+
+ if (!t_conf_done) {
+ config_timers();
+ start_timers();
+ }
+ /* gpio_set_value(MOD,1); */
+ }
+
+ return 0;
+}
+
+static int bfin_lq035_fb_release(struct fb_info *info, int user)
+{
+ unsigned long flags;
+
+ spin_lock_irqsave(&bfin_lq035_lock, flags);
+ lq035_open_cnt--;
+ spin_unlock_irqrestore(&bfin_lq035_lock, flags);
+
+
+ if (lq035_open_cnt <= 0) {
+
+ bfin_write_PPI_CONTROL(0);
+ SSYNC();
+
+ disable_dma(CH_PPI);
+ }
+
+ return 0;
+}
+
+
+static int bfin_lq035_fb_check_var(struct fb_var_screeninfo *var,
+ struct fb_info *info)
+{
+ switch (var->bits_per_pixel) {
+ case 16:/* DIRECTCOLOUR, 64k */
+ var->red.offset = info->var.red.offset;
+ var->green.offset = info->var.green.offset;
+ var->blue.offset = info->var.blue.offset;
+ var->red.length = info->var.red.length;
+ var->green.length = info->var.green.length;
+ var->blue.length = info->var.blue.length;
+ var->transp.offset = 0;
+ var->transp.length = 0;
+ var->transp.msb_right = 0;
+ var->red.msb_right = 0;
+ var->green.msb_right = 0;
+ var->blue.msb_right = 0;
+ break;
+ default:
+ pr_debug("%s: depth not supported: %u BPP\n", __func__,
+ var->bits_per_pixel);
+ return -EINVAL;
+ }
+
+ if (info->var.xres != var->xres ||
+ info->var.yres != var->yres ||
+ info->var.xres_virtual != var->xres_virtual ||
+ info->var.yres_virtual != var->yres_virtual) {
+ pr_debug("%s: Resolution not supported: X%u x Y%u\n",
+ __func__, var->xres, var->yres);
+ return -EINVAL;
+ }
+
+ /*
+ * Memory limit
+ */
+
+ if ((info->fix.line_length * var->yres_virtual) > info->fix.smem_len) {
+ pr_debug("%s: Memory Limit requested yres_virtual = %u\n",
+ __func__, var->yres_virtual);
+ return -ENOMEM;
+ }
+
+ return 0;
+}
+
+/* fb_rotate
+ * Rotate the display of this angle. This doesn't seems to be used by the core,
+ * but as our hardware supports it, so why not implementing it...
+ */
+static void bfin_lq035_fb_rotate(struct fb_info *fbi, int angle)
+{
+ pr_debug("%s: %p %d", __func__, fbi, angle);
+#if (defined(UD) && defined(LBR))
+ switch (angle) {
+
+ case 180:
+ gpio_set_value(LBR, 0);
+ gpio_set_value(UD, 1);
+ break;
+ default:
+ gpio_set_value(LBR, 1);
+ gpio_set_value(UD, 0);
+ break;
+ }
+#endif
+}
+
+static int bfin_lq035_fb_cursor(struct fb_info *info, struct fb_cursor *cursor)
+{
+ if (nocursor)
+ return 0;
+ else
+ return -EINVAL; /* just to force soft_cursor() call */
+}
+
+static int bfin_lq035_fb_setcolreg(u_int regno, u_int red, u_int green,
+ u_int blue, u_int transp,
+ struct fb_info *info)
+{
+ if (regno >= NBR_PALETTE)
+ return -EINVAL;
+
+ if (info->var.grayscale)
+ /* grayscale = 0.30*R + 0.59*G + 0.11*B */
+ red = green = blue = (red * 77 + green * 151 + blue * 28) >> 8;
+
+ if (info->fix.visual == FB_VISUAL_TRUECOLOR) {
+
+ u32 value;
+ /* Place color in the pseudopalette */
+ if (regno > 16)
+ return -EINVAL;
+
+ red >>= (16 - info->var.red.length);
+ green >>= (16 - info->var.green.length);
+ blue >>= (16 - info->var.blue.length);
+
+ value = (red << info->var.red.offset) |
+ (green << info->var.green.offset)|
+ (blue << info->var.blue.offset);
+ value &= 0xFFFF;
+
+ ((u32 *) (info->pseudo_palette))[regno] = value;
+
+ }
+
+ return 0;
+}
+
+static struct fb_ops bfin_lq035_fb_ops = {
+ .owner = THIS_MODULE,
+ .fb_open = bfin_lq035_fb_open,
+ .fb_release = bfin_lq035_fb_release,
+ .fb_check_var = bfin_lq035_fb_check_var,
+ .fb_rotate = bfin_lq035_fb_rotate,
+ .fb_fillrect = cfb_fillrect,
+ .fb_copyarea = cfb_copyarea,
+ .fb_imageblit = cfb_imageblit,
+ .fb_cursor = bfin_lq035_fb_cursor,
+ .fb_setcolreg = bfin_lq035_fb_setcolreg,
+};
+
+static int bl_get_brightness(struct backlight_device *bd)
+{
+ return current_brightness;
+}
+
+static const struct backlight_ops bfin_lq035fb_bl_ops = {
+ .get_brightness = bl_get_brightness,
+};
+
+static struct backlight_device *bl_dev;
+
+static int bfin_lcd_get_power(struct lcd_device *dev)
+{
+ return 0;
+}
+
+static int bfin_lcd_set_power(struct lcd_device *dev, int power)
+{
+ return 0;
+}
+
+static int bfin_lcd_get_contrast(struct lcd_device *dev)
+{
+ return (int)vcomm_value;
+}
+
+static int bfin_lcd_set_contrast(struct lcd_device *dev, int contrast)
+{
+ if (contrast > 255)
+ contrast = 255;
+ if (contrast < 0)
+ contrast = 0;
+
+ vcomm_value = (unsigned char)contrast;
+ set_vcomm();
+ return 0;
+}
+
+static int bfin_lcd_check_fb(struct lcd_device *lcd, struct fb_info *fi)
+{
+ if (!fi || (fi == &bfin_lq035_fb))
+ return 1;
+ return 0;
+}
+
+static struct lcd_ops bfin_lcd_ops = {
+ .get_power = bfin_lcd_get_power,
+ .set_power = bfin_lcd_set_power,
+ .get_contrast = bfin_lcd_get_contrast,
+ .set_contrast = bfin_lcd_set_contrast,
+ .check_fb = bfin_lcd_check_fb,
+};
+
+static struct lcd_device *lcd_dev;
+
+static int __devinit bfin_lq035_probe(struct platform_device *pdev)
+{
+ struct backlight_properties props;
+ dma_addr_t dma_handle;
+
+ if (request_dma(CH_PPI, KBUILD_MODNAME)) {
+ pr_err("couldn't request PPI DMA\n");
+ return -EFAULT;
+ }
+
+ if (request_ports()) {
+ pr_err("couldn't request gpio port\n");
+ free_dma(CH_PPI);
+ return -EFAULT;
+ }
+
+ fb_buffer = dma_alloc_coherent(NULL, TOTAL_VIDEO_MEM_SIZE,
+ &dma_handle, GFP_KERNEL);
+ if (fb_buffer == NULL) {
+ pr_err("couldn't allocate dma buffer\n");
+ free_dma(CH_PPI);
+ free_ports();
+ return -ENOMEM;
+ }
+
+ if (L1_DATA_A_LENGTH)
+ dma_desc_table = l1_data_sram_zalloc(TOTAL_DMA_DESC_SIZE);
+ else
+ dma_desc_table = dma_alloc_coherent(NULL, TOTAL_DMA_DESC_SIZE,
+ &dma_handle, 0);
+
+ if (dma_desc_table == NULL) {
+ pr_err("couldn't allocate dma descriptor\n");
+ free_dma(CH_PPI);
+ free_ports();
+ dma_free_coherent(NULL, TOTAL_VIDEO_MEM_SIZE, fb_buffer, 0);
+ return -ENOMEM;
+ }
+
+ bfin_lq035_fb.screen_base = (void *)fb_buffer;
+ bfin_lq035_fb_fix.smem_start = (int)fb_buffer;
+ if (landscape) {
+ bfin_lq035_fb_defined.xres = LCD_Y_RES;
+ bfin_lq035_fb_defined.yres = LCD_X_RES;
+ bfin_lq035_fb_defined.xres_virtual = LCD_Y_RES;
+ bfin_lq035_fb_defined.yres_virtual = LCD_X_RES;
+
+ bfin_lq035_fb_fix.line_length = LCD_Y_RES*(LCD_BBP/8);
+ } else {
+ bfin_lq035_fb.screen_base += ACTIVE_VIDEO_MEM_OFFSET;
+ bfin_lq035_fb_fix.smem_start += ACTIVE_VIDEO_MEM_OFFSET;
+ }
+
+ bfin_lq035_fb_defined.green.msb_right = 0;
+ bfin_lq035_fb_defined.red.msb_right = 0;
+ bfin_lq035_fb_defined.blue.msb_right = 0;
+ bfin_lq035_fb_defined.green.offset = 5;
+ bfin_lq035_fb_defined.green.length = 6;
+ bfin_lq035_fb_defined.red.length = 5;
+ bfin_lq035_fb_defined.blue.length = 5;
+
+ if (bgr) {
+ bfin_lq035_fb_defined.red.offset = 0;
+ bfin_lq035_fb_defined.blue.offset = 11;
+ } else {
+ bfin_lq035_fb_defined.red.offset = 11;
+ bfin_lq035_fb_defined.blue.offset = 0;
+ }
+
+ bfin_lq035_fb.fbops = &bfin_lq035_fb_ops;
+ bfin_lq035_fb.var = bfin_lq035_fb_defined;
+
+ bfin_lq035_fb.fix = bfin_lq035_fb_fix;
+ bfin_lq035_fb.flags = FBINFO_DEFAULT;
+
+
+ bfin_lq035_fb.pseudo_palette = kzalloc(sizeof(u32) * 16, GFP_KERNEL);
+ if (bfin_lq035_fb.pseudo_palette == NULL) {
+ pr_err("failed to allocate pseudo_palette\n");
+ free_dma(CH_PPI);
+ free_ports();
+ dma_free_coherent(NULL, TOTAL_VIDEO_MEM_SIZE, fb_buffer, 0);
+ return -ENOMEM;
+ }
+
+ if (fb_alloc_cmap(&bfin_lq035_fb.cmap, NBR_PALETTE, 0) < 0) {
+ pr_err("failed to allocate colormap (%d entries)\n",
+ NBR_PALETTE);
+ free_dma(CH_PPI);
+ free_ports();
+ dma_free_coherent(NULL, TOTAL_VIDEO_MEM_SIZE, fb_buffer, 0);
+ kfree(bfin_lq035_fb.pseudo_palette);
+ return -EFAULT;
+ }
+
+ if (register_framebuffer(&bfin_lq035_fb) < 0) {
+ pr_err("unable to register framebuffer\n");
+ free_dma(CH_PPI);
+ free_ports();
+ dma_free_coherent(NULL, TOTAL_VIDEO_MEM_SIZE, fb_buffer, 0);
+ fb_buffer = NULL;
+ kfree(bfin_lq035_fb.pseudo_palette);
+ fb_dealloc_cmap(&bfin_lq035_fb.cmap);
+ return -EINVAL;
+ }
+
+ i2c_add_driver(&ad5280_driver);
+
+ memset(&props, 0, sizeof(props));
+ props.max_brightness = MAX_BRIGHENESS;
+ bl_dev = backlight_device_register("bf537-bl", NULL, NULL,
+ &bfin_lq035fb_bl_ops, &props);
+
+ lcd_dev = lcd_device_register(KBUILD_MODNAME, &pdev->dev, NULL,
+ &bfin_lcd_ops);
+ lcd_dev->props.max_contrast = 255,
+
+ pr_info("initialized");
+
+ return 0;
+}
+
+static int __devexit bfin_lq035_remove(struct platform_device *pdev)
+{
+ if (fb_buffer != NULL)
+ dma_free_coherent(NULL, TOTAL_VIDEO_MEM_SIZE, fb_buffer, 0);
+
+ if (L1_DATA_A_LENGTH)
+ l1_data_sram_free(dma_desc_table);
+ else
+ dma_free_coherent(NULL, TOTAL_DMA_DESC_SIZE, NULL, 0);
+
+ bfin_write_TIMER_DISABLE(TIMEN_SP|TIMEN_SPS|TIMEN_PS_CLS|
+ TIMEN_LP|TIMEN_REV);
+ t_conf_done = 0;
+
+ free_dma(CH_PPI);
+
+
+ kfree(bfin_lq035_fb.pseudo_palette);
+ fb_dealloc_cmap(&bfin_lq035_fb.cmap);
+
+
+ lcd_device_unregister(lcd_dev);
+ backlight_device_unregister(bl_dev);
+
+ unregister_framebuffer(&bfin_lq035_fb);
+ i2c_del_driver(&ad5280_driver);
+
+ free_ports();
+
+ pr_info("unregistered LCD driver\n");
+
+ return 0;
+}
+
+#ifdef CONFIG_PM
+static int bfin_lq035_suspend(struct platform_device *pdev, pm_message_t state)
+{
+ if (lq035_open_cnt > 0) {
+ bfin_write_PPI_CONTROL(0);
+ SSYNC();
+ disable_dma(CH_PPI);
+ }
+
+ return 0;
+}
+
+static int bfin_lq035_resume(struct platform_device *pdev)
+{
+ if (lq035_open_cnt > 0) {
+ bfin_write_PPI_CONTROL(0);
+ SSYNC();
+
+ config_dma();
+ config_ppi();
+
+ enable_dma(CH_PPI);
+ bfin_write_PPI_CONTROL(bfin_read_PPI_CONTROL() | PORT_EN);
+ SSYNC();
+
+ config_timers();
+ start_timers();
+ } else {
+ t_conf_done = 0;
+ }
+
+ return 0;
+}
+#else
+# define bfin_lq035_suspend NULL
+# define bfin_lq035_resume NULL
+#endif
+
+static struct platform_driver bfin_lq035_driver = {
+ .probe = bfin_lq035_probe,
+ .remove = __devexit_p(bfin_lq035_remove),
+ .suspend = bfin_lq035_suspend,
+ .resume = bfin_lq035_resume,
+ .driver = {
+ .name = KBUILD_MODNAME,
+ .owner = THIS_MODULE,
+ },
+};
+
+static int __init bfin_lq035_driver_init(void)
+{
+ request_module("i2c-bfin-twi");
+ return platform_driver_register(&bfin_lq035_driver);
+}
+module_init(bfin_lq035_driver_init);
+
+static void __exit bfin_lq035_driver_cleanup(void)
+{
+ platform_driver_unregister(&bfin_lq035_driver);
+}
+module_exit(bfin_lq035_driver_cleanup);
+
+MODULE_DESCRIPTION("SHARP LQ035Q7DB03 TFT LCD Driver");
+MODULE_LICENSE("GPL");
--- /dev/null
+/*
+ * Frame buffer driver for ADV7393/2 video encoder
+ *
+ * Copyright 2006-2009 Analog Devices Inc.
+ * Licensed under the GPL-2 or late.
+ */
+
+/*
+ * TODO: Remove Globals
+ * TODO: Code Cleanup
+ */
+
+#define pr_fmt(fmt) DRIVER_NAME ": " fmt
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/errno.h>
+#include <linux/string.h>
+#include <linux/mm.h>
+#include <linux/tty.h>
+#include <linux/slab.h>
+#include <linux/delay.h>
+#include <linux/fb.h>
+#include <linux/ioport.h>
+#include <linux/init.h>
+#include <linux/types.h>
+#include <linux/interrupt.h>
+#include <linux/sched.h>
+#include <asm/blackfin.h>
+#include <asm/irq.h>
+#include <asm/dma.h>
+#include <linux/uaccess.h>
+#include <linux/gpio.h>
+#include <asm/portmux.h>
+
+#include <linux/dma-mapping.h>
+#include <linux/proc_fs.h>
+#include <linux/platform_device.h>
+
+#include <linux/i2c.h>
+#include <linux/i2c-dev.h>
+
+#include "bfin_adv7393fb.h"
+
+static int mode = VMODE;
+static int mem = VMEM;
+static int nocursor = 1;
+
+static const unsigned short ppi_pins[] = {
+ P_PPI0_CLK, P_PPI0_FS1, P_PPI0_FS2,
+ P_PPI0_D0, P_PPI0_D1, P_PPI0_D2, P_PPI0_D3,
+ P_PPI0_D4, P_PPI0_D5, P_PPI0_D6, P_PPI0_D7,
+ P_PPI0_D8, P_PPI0_D9, P_PPI0_D10, P_PPI0_D11,
+ P_PPI0_D12, P_PPI0_D13, P_PPI0_D14, P_PPI0_D15,
+ 0
+};
+
+/*
+ * card parameters
+ */
+
+static struct bfin_adv7393_fb_par {
+ /* structure holding blackfin / adv7393 paramters when
+ screen is blanked */
+ struct {
+ u8 Mode; /* ntsc/pal/? */
+ } vga_state;
+ atomic_t ref_count;
+} bfin_par;
+
+/* --------------------------------------------------------------------- */
+
+static struct fb_var_screeninfo bfin_adv7393_fb_defined = {
+ .xres = 720,
+ .yres = 480,
+ .xres_virtual = 720,
+ .yres_virtual = 480,
+ .bits_per_pixel = 16,
+ .activate = FB_ACTIVATE_TEST,
+ .height = -1,
+ .width = -1,
+ .left_margin = 0,
+ .right_margin = 0,
+ .upper_margin = 0,
+ .lower_margin = 0,
+ .vmode = FB_VMODE_INTERLACED,
+ .red = {11, 5, 0},
+ .green = {5, 6, 0},
+ .blue = {0, 5, 0},
+ .transp = {0, 0, 0},
+};
+
+static struct fb_fix_screeninfo bfin_adv7393_fb_fix __devinitdata = {
+ .id = "BFIN ADV7393",
+ .smem_len = 720 * 480 * 2,
+ .type = FB_TYPE_PACKED_PIXELS,
+ .visual = FB_VISUAL_TRUECOLOR,
+ .xpanstep = 0,
+ .ypanstep = 0,
+ .line_length = 720 * 2,
+ .accel = FB_ACCEL_NONE
+};
+
+static struct fb_ops bfin_adv7393_fb_ops = {
+ .owner = THIS_MODULE,
+ .fb_open = bfin_adv7393_fb_open,
+ .fb_release = bfin_adv7393_fb_release,
+ .fb_check_var = bfin_adv7393_fb_check_var,
+ .fb_pan_display = bfin_adv7393_fb_pan_display,
+ .fb_blank = bfin_adv7393_fb_blank,
+ .fb_fillrect = cfb_fillrect,
+ .fb_copyarea = cfb_copyarea,
+ .fb_imageblit = cfb_imageblit,
+ .fb_cursor = bfin_adv7393_fb_cursor,
+ .fb_setcolreg = bfin_adv7393_fb_setcolreg,
+};
+
+static int dma_desc_list(struct adv7393fb_device *fbdev, u16 arg)
+{
+ if (arg == BUILD) { /* Build */
+ fbdev->vb1 = l1_data_sram_zalloc(sizeof(struct dmasg));
+ if (fbdev->vb1 == NULL)
+ goto error;
+
+ fbdev->av1 = l1_data_sram_zalloc(sizeof(struct dmasg));
+ if (fbdev->av1 == NULL)
+ goto error;
+
+ fbdev->vb2 = l1_data_sram_zalloc(sizeof(struct dmasg));
+ if (fbdev->vb2 == NULL)
+ goto error;
+
+ fbdev->av2 = l1_data_sram_zalloc(sizeof(struct dmasg));
+ if (fbdev->av2 == NULL)
+ goto error;
+
+ /* Build linked DMA descriptor list */
+ fbdev->vb1->next_desc_addr = fbdev->av1;
+ fbdev->av1->next_desc_addr = fbdev->vb2;
+ fbdev->vb2->next_desc_addr = fbdev->av2;
+ fbdev->av2->next_desc_addr = fbdev->vb1;
+
+ /* Save list head */
+ fbdev->descriptor_list_head = fbdev->av2;
+
+ /* Vertical Blanking Field 1 */
+ fbdev->vb1->start_addr = VB_DUMMY_MEMORY_SOURCE;
+ fbdev->vb1->cfg = DMA_CFG_VAL;
+
+ fbdev->vb1->x_count =
+ fbdev->modes[mode].xres + fbdev->modes[mode].boeft_blank;
+
+ fbdev->vb1->x_modify = 0;
+ fbdev->vb1->y_count = fbdev->modes[mode].vb1_lines;
+ fbdev->vb1->y_modify = 0;
+
+ /* Active Video Field 1 */
+
+ fbdev->av1->start_addr = (unsigned long)fbdev->fb_mem;
+ fbdev->av1->cfg = DMA_CFG_VAL;
+ fbdev->av1->x_count =
+ fbdev->modes[mode].xres + fbdev->modes[mode].boeft_blank;
+ fbdev->av1->x_modify = fbdev->modes[mode].bpp / 8;
+ fbdev->av1->y_count = fbdev->modes[mode].a_lines;
+ fbdev->av1->y_modify =
+ (fbdev->modes[mode].xres - fbdev->modes[mode].boeft_blank +
+ 1) * (fbdev->modes[mode].bpp / 8);
+
+ /* Vertical Blanking Field 2 */
+
+ fbdev->vb2->start_addr = VB_DUMMY_MEMORY_SOURCE;
+ fbdev->vb2->cfg = DMA_CFG_VAL;
+ fbdev->vb2->x_count =
+ fbdev->modes[mode].xres + fbdev->modes[mode].boeft_blank;
+
+ fbdev->vb2->x_modify = 0;
+ fbdev->vb2->y_count = fbdev->modes[mode].vb2_lines;
+ fbdev->vb2->y_modify = 0;
+
+ /* Active Video Field 2 */
+
+ fbdev->av2->start_addr =
+ (unsigned long)fbdev->fb_mem + fbdev->line_len;
+
+ fbdev->av2->cfg = DMA_CFG_VAL;
+
+ fbdev->av2->x_count =
+ fbdev->modes[mode].xres + fbdev->modes[mode].boeft_blank;
+
+ fbdev->av2->x_modify = (fbdev->modes[mode].bpp / 8);
+ fbdev->av2->y_count = fbdev->modes[mode].a_lines;
+
+ fbdev->av2->y_modify =
+ (fbdev->modes[mode].xres - fbdev->modes[mode].boeft_blank +
+ 1) * (fbdev->modes[mode].bpp / 8);
+
+ return 1;
+ }
+
+error:
+ l1_data_sram_free(fbdev->vb1);
+ l1_data_sram_free(fbdev->av1);
+ l1_data_sram_free(fbdev->vb2);
+ l1_data_sram_free(fbdev->av2);
+
+ return 0;
+}
+
+static int bfin_config_dma(struct adv7393fb_device *fbdev)
+{
+ BUG_ON(!(fbdev->fb_mem));
+
+ set_dma_x_count(CH_PPI, fbdev->descriptor_list_head->x_count);
+ set_dma_x_modify(CH_PPI, fbdev->descriptor_list_head->x_modify);
+ set_dma_y_count(CH_PPI, fbdev->descriptor_list_head->y_count);
+ set_dma_y_modify(CH_PPI, fbdev->descriptor_list_head->y_modify);
+ set_dma_start_addr(CH_PPI, fbdev->descriptor_list_head->start_addr);
+ set_dma_next_desc_addr(CH_PPI,
+ fbdev->descriptor_list_head->next_desc_addr);
+ set_dma_config(CH_PPI, fbdev->descriptor_list_head->cfg);
+
+ return 1;
+}
+
+static void bfin_disable_dma(void)
+{
+ bfin_write_DMA0_CONFIG(bfin_read_DMA0_CONFIG() & ~DMAEN);
+}
+
+static void bfin_config_ppi(struct adv7393fb_device *fbdev)
+{
+ if (ANOMALY_05000183) {
+ bfin_write_TIMER2_CONFIG(WDTH_CAP);
+ bfin_write_TIMER_ENABLE(TIMEN2);
+ }
+
+ bfin_write_PPI_CONTROL(0x381E);
+ bfin_write_PPI_FRAME(fbdev->modes[mode].tot_lines);
+ bfin_write_PPI_COUNT(fbdev->modes[mode].xres +
+ fbdev->modes[mode].boeft_blank - 1);
+ bfin_write_PPI_DELAY(fbdev->modes[mode].aoeft_blank - 1);
+}
+
+static void bfin_enable_ppi(void)
+{
+ bfin_write_PPI_CONTROL(bfin_read_PPI_CONTROL() | PORT_EN);
+}
+
+static void bfin_disable_ppi(void)
+{
+ bfin_write_PPI_CONTROL(bfin_read_PPI_CONTROL() & ~PORT_EN);
+}
+
+static inline int adv7393_write(struct i2c_client *client, u8 reg, u8 value)
+{
+ return i2c_smbus_write_byte_data(client, reg, value);
+}
+
+static inline int adv7393_read(struct i2c_client *client, u8 reg)
+{
+ return i2c_smbus_read_byte_data(client, reg);
+}
+
+static int
+adv7393_write_block(struct i2c_client *client,
+ const u8 *data, unsigned int len)
+{
+ int ret = -1;
+ u8 reg;
+
+ while (len >= 2) {
+ reg = *data++;
+ ret = adv7393_write(client, reg, *data++);
+ if (ret < 0)
+ break;
+ len -= 2;
+ }
+
+ return ret;
+}
+
+static int adv7393_mode(struct i2c_client *client, u16 mode)
+{
+ switch (mode) {
+ case POWER_ON: /* ADV7393 Sleep mode OFF */
+ adv7393_write(client, 0x00, 0x1E);
+ break;
+ case POWER_DOWN: /* ADV7393 Sleep mode ON */
+ adv7393_write(client, 0x00, 0x1F);
+ break;
+ case BLANK_OFF: /* Pixel Data Valid */
+ adv7393_write(client, 0x82, 0xCB);
+ break;
+ case BLANK_ON: /* Pixel Data Invalid */
+ adv7393_write(client, 0x82, 0x8B);
+ break;
+ default:
+ return -EINVAL;
+ break;
+ }
+ return 0;
+}
+
+static irqreturn_t ppi_irq_error(int irq, void *dev_id)
+{
+
+ struct adv7393fb_device *fbdev = (struct adv7393fb_device *)dev_id;
+
+ u16 status = bfin_read_PPI_STATUS();
+
+ pr_debug("%s: PPI Status = 0x%X\n", __func__, status);
+
+ if (status) {
+ bfin_disable_dma(); /* TODO: Check Sequence */
+ bfin_disable_ppi();
+ bfin_clear_PPI_STATUS();
+ bfin_config_dma(fbdev);
+ bfin_enable_ppi();
+ }
+
+ return IRQ_HANDLED;
+
+}
+
+static int proc_output(char *buf)
+{
+ char *p = buf;
+
+ p += sprintf(p,
+ "Usage:\n"
+ "echo 0x[REG][Value] > adv7393\n"
+ "example: echo 0x1234 >adv7393\n"
+ "writes 0x34 into Register 0x12\n");
+
+ return p - buf;
+}
+
+static int
+adv7393_read_proc(char *page, char **start, off_t off,
+ int count, int *eof, void *data)
+{
+ int len;
+
+ len = proc_output(page);
+ if (len <= off + count)
+ *eof = 1;
+ *start = page + off;
+ len -= off;
+ if (len > count)
+ len = count;
+ if (len < 0)
+ len = 0;
+ return len;
+}
+
+static int
+adv7393_write_proc(struct file *file, const char __user * buffer,
+ unsigned long count, void *data)
+{
+ struct adv7393fb_device *fbdev = data;
+ char line[8];
+ unsigned int val;
+ int ret;
+
+ ret = copy_from_user(line, buffer, count);
+ if (ret)
+ return -EFAULT;
+
+ val = simple_strtoul(line, NULL, 0);
+ adv7393_write(fbdev->client, val >> 8, val & 0xff);
+
+ return count;
+}
+
+static int __devinit bfin_adv7393_fb_probe(struct i2c_client *client,
+ const struct i2c_device_id *id)
+{
+ int ret = 0;
+ struct proc_dir_entry *entry;
+ int num_modes = ARRAY_SIZE(known_modes);
+
+ struct adv7393fb_device *fbdev = NULL;
+
+ if (mem > 2) {
+ dev_err(&client->dev, "mem out of allowed range [1;2]\n");
+ return -EINVAL;
+ }
+
+ if (mode > num_modes) {
+ dev_err(&client->dev, "mode %d: not supported", mode);
+ return -EFAULT;
+ }
+
+ fbdev = kzalloc(sizeof(*fbdev), GFP_KERNEL);
+ if (!fbdev) {
+ dev_err(&client->dev, "failed to allocate device private record");
+ return -ENOMEM;
+ }
+
+ i2c_set_clientdata(client, fbdev);
+
+ fbdev->modes = known_modes;
+ fbdev->client = client;
+
+ fbdev->fb_len =
+ mem * fbdev->modes[mode].xres * fbdev->modes[mode].xres *
+ (fbdev->modes[mode].bpp / 8);
+
+ fbdev->line_len =
+ fbdev->modes[mode].xres * (fbdev->modes[mode].bpp / 8);
+
+ /* Workaround "PPI Does Not Start Properly In Specific Mode" */
+ if (ANOMALY_05000400) {
+ if (gpio_request(P_IDENT(P_PPI0_FS3), "PPI0_FS3")) {
+ dev_err(&client->dev, "PPI0_FS3 GPIO request failed\n");
+ ret = -EBUSY;
+ goto out_8;
+ }
+ gpio_direction_output(P_IDENT(P_PPI0_FS3), 0);
+ }
+
+ if (peripheral_request_list(ppi_pins, DRIVER_NAME)) {
+ dev_err(&client->dev, "requesting PPI peripheral failed\n");
+ ret = -EFAULT;
+ goto out_8;
+ }
+
+ fbdev->fb_mem =
+ dma_alloc_coherent(NULL, fbdev->fb_len, &fbdev->dma_handle,
+ GFP_KERNEL);
+
+ if (NULL == fbdev->fb_mem) {
+ dev_err(&client->dev, "couldn't allocate dma buffer (%d bytes)\n",
+ (u32) fbdev->fb_len);
+ ret = -ENOMEM;
+ goto out_7;
+ }
+
+ fbdev->info.screen_base = (void *)fbdev->fb_mem;
+ bfin_adv7393_fb_fix.smem_start = (int)fbdev->fb_mem;
+
+ bfin_adv7393_fb_fix.smem_len = fbdev->fb_len;
+ bfin_adv7393_fb_fix.line_length = fbdev->line_len;
+
+ if (mem > 1)
+ bfin_adv7393_fb_fix.ypanstep = 1;
+
+ bfin_adv7393_fb_defined.red.length = 5;
+ bfin_adv7393_fb_defined.green.length = 6;
+ bfin_adv7393_fb_defined.blue.length = 5;
+
+ bfin_adv7393_fb_defined.xres = fbdev->modes[mode].xres;
+ bfin_adv7393_fb_defined.yres = fbdev->modes[mode].yres;
+ bfin_adv7393_fb_defined.xres_virtual = fbdev->modes[mode].xres;
+ bfin_adv7393_fb_defined.yres_virtual = mem * fbdev->modes[mode].yres;
+ bfin_adv7393_fb_defined.bits_per_pixel = fbdev->modes[mode].bpp;
+
+ fbdev->info.fbops = &bfin_adv7393_fb_ops;
+ fbdev->info.var = bfin_adv7393_fb_defined;
+ fbdev->info.fix = bfin_adv7393_fb_fix;
+ fbdev->info.par = &bfin_par;
+ fbdev->info.flags = FBINFO_DEFAULT;
+
+ fbdev->info.pseudo_palette = kzalloc(sizeof(u32) * 16, GFP_KERNEL);
+ if (!fbdev->info.pseudo_palette) {
+ dev_err(&client->dev, "failed to allocate pseudo_palette\n");
+ ret = -ENOMEM;
+ goto out_6;
+ }
+
+ if (fb_alloc_cmap(&fbdev->info.cmap, BFIN_LCD_NBR_PALETTE_ENTRIES, 0) < 0) {
+ dev_err(&client->dev, "failed to allocate colormap (%d entries)\n",
+ BFIN_LCD_NBR_PALETTE_ENTRIES);
+ ret = -EFAULT;
+ goto out_5;
+ }
+
+ if (request_dma(CH_PPI, "BF5xx_PPI_DMA") < 0) {
+ dev_err(&client->dev, "unable to request PPI DMA\n");
+ ret = -EFAULT;
+ goto out_4;
+ }
+
+ if (request_irq(IRQ_PPI_ERROR, ppi_irq_error, IRQF_DISABLED,
+ "PPI ERROR", fbdev) < 0) {
+ dev_err(&client->dev, "unable to request PPI ERROR IRQ\n");
+ ret = -EFAULT;
+ goto out_3;
+ }
+
+ fbdev->open = 0;
+
+ ret = adv7393_write_block(client, fbdev->modes[mode].adv7393_i2c_initd,
+ fbdev->modes[mode].adv7393_i2c_initd_len);
+
+ if (ret) {
+ dev_err(&client->dev, "i2c attach: init error\n");
+ goto out_1;
+ }
+
+
+ if (register_framebuffer(&fbdev->info) < 0) {
+ dev_err(&client->dev, "unable to register framebuffer\n");
+ ret = -EFAULT;
+ goto out_1;
+ }
+
+ dev_info(&client->dev, "fb%d: %s frame buffer device\n",
+ fbdev->info.node, fbdev->info.fix.id);
+ dev_info(&client->dev, "fb memory address : 0x%p\n", fbdev->fb_mem);
+
+ entry = create_proc_entry("driver/adv7393", 0, NULL);
+ if (!entry) {
+ dev_err(&client->dev, "unable to create /proc entry\n");
+ ret = -EFAULT;
+ goto out_0;
+ }
+
+ entry->read_proc = adv7393_read_proc;
+ entry->write_proc = adv7393_write_proc;
+ entry->data = fbdev;
+
+ return 0;
+
+ out_0:
+ unregister_framebuffer(&fbdev->info);
+ out_1:
+ free_irq(IRQ_PPI_ERROR, fbdev);
+ out_3:
+ free_dma(CH_PPI);
+ out_4:
+ dma_free_coherent(NULL, fbdev->fb_len, fbdev->fb_mem,
+ fbdev->dma_handle);
+ out_5:
+ fb_dealloc_cmap(&fbdev->info.cmap);
+ out_6:
+ kfree(fbdev->info.pseudo_palette);
+ out_7:
+ peripheral_free_list(ppi_pins);
+ out_8:
+ kfree(fbdev);
+
+ return ret;
+}
+
+static int bfin_adv7393_fb_open(struct fb_info *info, int user)
+{
+ struct adv7393fb_device *fbdev = to_adv7393fb_device(info);
+
+ fbdev->info.screen_base = (void *)fbdev->fb_mem;
+ if (!fbdev->info.screen_base) {
+ dev_err(&fbdev->client->dev, "unable to map device\n");
+ return -ENOMEM;
+ }
+
+ fbdev->open = 1;
+ dma_desc_list(fbdev, BUILD);
+ adv7393_mode(fbdev->client, BLANK_OFF);
+ bfin_config_ppi(fbdev);
+ bfin_config_dma(fbdev);
+ bfin_enable_ppi();
+
+ return 0;
+}
+
+static int bfin_adv7393_fb_release(struct fb_info *info, int user)
+{
+ struct adv7393fb_device *fbdev = to_adv7393fb_device(info);
+
+ adv7393_mode(fbdev->client, BLANK_ON);
+ bfin_disable_dma();
+ bfin_disable_ppi();
+ dma_desc_list(fbdev, DESTRUCT);
+ fbdev->open = 0;
+ return 0;
+}
+
+static int
+bfin_adv7393_fb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
+{
+
+ switch (var->bits_per_pixel) {
+ case 16:/* DIRECTCOLOUR, 64k */
+ var->red.offset = info->var.red.offset;
+ var->green.offset = info->var.green.offset;
+ var->blue.offset = info->var.blue.offset;
+ var->red.length = info->var.red.length;
+ var->green.length = info->var.green.length;
+ var->blue.length = info->var.blue.length;
+ var->transp.offset = 0;
+ var->transp.length = 0;
+ var->transp.msb_right = 0;
+ var->red.msb_right = 0;
+ var->green.msb_right = 0;
+ var->blue.msb_right = 0;
+ break;
+ default:
+ pr_debug("%s: depth not supported: %u BPP\n", __func__,
+ var->bits_per_pixel);
+ return -EINVAL;
+ }
+
+ if (info->var.xres != var->xres ||
+ info->var.yres != var->yres ||
+ info->var.xres_virtual != var->xres_virtual ||
+ info->var.yres_virtual != var->yres_virtual) {
+ pr_debug("%s: Resolution not supported: X%u x Y%u\n",
+ __func__, var->xres, var->yres);
+ return -EINVAL;
+ }
+
+ /*
+ * Memory limit
+ */
+
+ if ((info->fix.line_length * var->yres_virtual) > info->fix.smem_len) {
+ pr_debug("%s: Memory Limit requested yres_virtual = %u\n",
+ __func__, var->yres_virtual);
+ return -ENOMEM;
+ }
+
+ return 0;
+}
+
+static int
+bfin_adv7393_fb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info)
+{
+ int dy;
+ u32 dmaaddr;
+ struct adv7393fb_device *fbdev = to_adv7393fb_device(info);
+
+ if (!var || !info)
+ return -EINVAL;
+
+ if (var->xoffset - info->var.xoffset) {
+ /* No support for X panning for now! */
+ return -EINVAL;
+ }
+ dy = var->yoffset - info->var.yoffset;
+
+ if (dy) {
+ pr_debug("%s: Panning screen of %d lines\n", __func__, dy);
+
+ dmaaddr = fbdev->av1->start_addr;
+ dmaaddr += (info->fix.line_length * dy);
+ /* TODO: Wait for current frame to finished */
+
+ fbdev->av1->start_addr = (unsigned long)dmaaddr;
+ fbdev->av2->start_addr = (unsigned long)dmaaddr + fbdev->line_len;
+ }
+
+ return 0;
+
+}
+
+/* 0 unblank, 1 blank, 2 no vsync, 3 no hsync, 4 off */
+static int bfin_adv7393_fb_blank(int blank, struct fb_info *info)
+{
+ struct adv7393fb_device *fbdev = to_adv7393fb_device(info);
+
+ switch (blank) {
+
+ case VESA_NO_BLANKING:
+ /* Turn on panel */
+ adv7393_mode(fbdev->client, BLANK_OFF);
+ break;
+
+ case VESA_VSYNC_SUSPEND:
+ case VESA_HSYNC_SUSPEND:
+ case VESA_POWERDOWN:
+ /* Turn off panel */
+ adv7393_mode(fbdev->client, BLANK_ON);
+ break;
+
+ default:
+ return -EINVAL;
+ break;
+ }
+ return 0;
+}
+
+int bfin_adv7393_fb_cursor(struct fb_info *info, struct fb_cursor *cursor)
+{
+ if (nocursor)
+ return 0;
+ else
+ return -EINVAL; /* just to force soft_cursor() call */
+}
+
+static int bfin_adv7393_fb_setcolreg(u_int regno, u_int red, u_int green,
+ u_int blue, u_int transp,
+ struct fb_info *info)
+{
+ if (regno >= BFIN_LCD_NBR_PALETTE_ENTRIES)
+ return -EINVAL;
+
+ if (info->var.grayscale)
+ /* grayscale = 0.30*R + 0.59*G + 0.11*B */
+ red = green = blue = (red * 77 + green * 151 + blue * 28) >> 8;
+
+ if (info->fix.visual == FB_VISUAL_TRUECOLOR) {
+ u32 value;
+ /* Place color in the pseudopalette */
+ if (regno > 16)
+ return -EINVAL;
+
+ red >>= (16 - info->var.red.length);
+ green >>= (16 - info->var.green.length);
+ blue >>= (16 - info->var.blue.length);
+
+ value = (red << info->var.red.offset) |
+ (green << info->var.green.offset)|
+ (blue << info->var.blue.offset);
+ value &= 0xFFFF;
+
+ ((u32 *) (info->pseudo_palette))[regno] = value;
+ }
+
+ return 0;
+}
+
+static int __devexit bfin_adv7393_fb_remove(struct i2c_client *client)
+{
+ struct adv7393fb_device *fbdev = i2c_get_clientdata(client);
+
+ adv7393_mode(client, POWER_DOWN);
+
+ if (fbdev->fb_mem)
+ dma_free_coherent(NULL, fbdev->fb_len, fbdev->fb_mem, fbdev->dma_handle);
+ free_dma(CH_PPI);
+ free_irq(IRQ_PPI_ERROR, fbdev);
+ unregister_framebuffer(&fbdev->info);
+ remove_proc_entry("driver/adv7393", NULL);
+ fb_dealloc_cmap(&fbdev->info.cmap);
+ kfree(fbdev->info.pseudo_palette);
+
+ if (ANOMALY_05000400)
+ gpio_free(P_IDENT(P_PPI0_FS3)); /* FS3 */
+ peripheral_free_list(ppi_pins);
+ kfree(fbdev);
+
+ return 0;
+}
+
+#ifdef CONFIG_PM
+static int bfin_adv7393_fb_suspend(struct device *dev)
+{
+ struct adv7393fb_device *fbdev = dev_get_drvdata(dev);
+
+ if (fbdev->open) {
+ bfin_disable_dma();
+ bfin_disable_ppi();
+ dma_desc_list(fbdev, DESTRUCT);
+ }
+ adv7393_mode(fbdev->client, POWER_DOWN);
+
+ return 0;
+}
+
+static int bfin_adv7393_fb_resume(struct device *dev)
+{
+ struct adv7393fb_device *fbdev = dev_get_drvdata(dev);
+
+ adv7393_mode(fbdev->client, POWER_ON);
+
+ if (fbdev->open) {
+ dma_desc_list(fbdev, BUILD);
+ bfin_config_ppi(fbdev);
+ bfin_config_dma(fbdev);
+ bfin_enable_ppi();
+ }
+
+ return 0;
+}
+
+static const struct dev_pm_ops bfin_adv7393_dev_pm_ops = {
+ .suspend = bfin_adv7393_fb_suspend,
+ .resume = bfin_adv7393_fb_resume,
+};
+#endif
+
+static const struct i2c_device_id bfin_adv7393_id[] = {
+ {DRIVER_NAME, 0},
+ {}
+};
+
+MODULE_DEVICE_TABLE(i2c, bfin_adv7393_id);
+
+static struct i2c_driver bfin_adv7393_fb_driver = {
+ .driver = {
+ .name = DRIVER_NAME,
+#ifdef CONFIG_PM
+ .pm = &bfin_adv7393_dev_pm_ops,
+#endif
+ },
+ .probe = bfin_adv7393_fb_probe,
+ .remove = __devexit_p(bfin_adv7393_fb_remove),
+ .id_table = bfin_adv7393_id,
+};
+
+static int __init bfin_adv7393_fb_driver_init(void)
+{
+#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
+ request_module("i2c-bfin-twi");
+#else
+ request_module("i2c-gpio");
+#endif
+
+ return i2c_add_driver(&bfin_adv7393_fb_driver);
+}
+module_init(bfin_adv7393_fb_driver_init);
+
+static void __exit bfin_adv7393_fb_driver_cleanup(void)
+{
+ i2c_del_driver(&bfin_adv7393_fb_driver);
+}
+module_exit(bfin_adv7393_fb_driver_cleanup);
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Michael Hennerich <hennerich@blackfin.uclinux.org>");
+MODULE_DESCRIPTION("Frame buffer driver for ADV7393/2 Video Encoder");
+
+module_param(mode, int, 0);
+MODULE_PARM_DESC(mode,
+ "Video Mode (0=NTSC,1=PAL,2=NTSC 640x480,3=PAL 640x480,4=NTSC YCbCr input,5=PAL YCbCr input)");
+
+module_param(mem, int, 0);
+MODULE_PARM_DESC(mem,
+ "Size of frame buffer memory 1=Single 2=Double Size (allows y-panning / frame stacking)");
+
+module_param(nocursor, int, 0644);
+MODULE_PARM_DESC(nocursor, "cursor enable/disable");
--- /dev/null
+/*
+ * Frame buffer driver for ADV7393/2 video encoder
+ *
+ * Copyright 2006-2009 Analog Devices Inc.
+ * Licensed under the GPL-2 or late.
+ */
+
+#ifndef __BFIN_ADV7393FB_H__
+#define __BFIN_ADV7393FB_H__
+
+#define BFIN_LCD_NBR_PALETTE_ENTRIES 256
+
+#ifdef CONFIG_NTSC
+# define VMODE 0
+#endif
+#ifdef CONFIG_PAL
+# define VMODE 1
+#endif
+#ifdef CONFIG_NTSC_640x480
+# define VMODE 2
+#endif
+#ifdef CONFIG_PAL_640x480
+# define VMODE 3
+#endif
+#ifdef CONFIG_NTSC_YCBCR
+# define VMODE 4
+#endif
+#ifdef CONFIG_PAL_YCBCR
+# define VMODE 5
+#endif
+
+#ifndef VMODE
+# define VMODE 1
+#endif
+
+#ifdef CONFIG_ADV7393_2XMEM
+# define VMEM 2
+#else
+# define VMEM 1
+#endif
+
+#if defined(CONFIG_BF537) || defined(CONFIG_BF536) || defined(CONFIG_BF534)
+# define DMA_CFG_VAL 0x7935 /* Set Sync Bit */
+# define VB_DUMMY_MEMORY_SOURCE L1_DATA_B_START
+#else
+# define DMA_CFG_VAL 0x7915
+# define VB_DUMMY_MEMORY_SOURCE BOOT_ROM_START
+#endif
+
+enum {
+ DESTRUCT,
+ BUILD,
+};
+
+enum {
+ POWER_ON,
+ POWER_DOWN,
+ BLANK_ON,
+ BLANK_OFF,
+};
+
+#define DRIVER_NAME "bfin-adv7393"
+
+struct adv7393fb_modes {
+ const s8 name[25]; /* Full name */
+ u16 xres; /* Active Horizonzal Pixels */
+ u16 yres; /* Active Vertical Pixels */
+ u16 bpp;
+ u16 vmode;
+ u16 a_lines; /* Active Lines per Field */
+ u16 vb1_lines; /* Vertical Blanking Field 1 Lines */
+ u16 vb2_lines; /* Vertical Blanking Field 2 Lines */
+ u16 tot_lines; /* Total Lines per Frame */
+ u16 boeft_blank; /* Before Odd/Even Field Transition No. of Blank Pixels */
+ u16 aoeft_blank; /* After Odd/Even Field Transition No. of Blank Pixels */
+ const s8 *adv7393_i2c_initd;
+ u16 adv7393_i2c_initd_len;
+};
+
+static const u8 init_NTSC_TESTPATTERN[] = {
+ 0x00, 0x1E, /* Power up all DACs and PLL */
+ 0x01, 0x00, /* SD-Only Mode */
+ 0x80, 0x10, /* SSAF Luma Filter Enabled, NTSC Mode */
+ 0x82, 0xCB, /* Step control on, pixel data valid, pedestal on, PrPb SSAF on, CVBS/YC output */
+ 0x84, 0x40, /* SD Color Bar Test Pattern Enabled, DAC 2 = Luma, DAC 3 = Chroma */
+};
+
+static const u8 init_NTSC[] = {
+ 0x00, 0x1E, /* Power up all DACs and PLL */
+ 0xC3, 0x26, /* Program RGB->YCrCb Color Space convertion matrix */
+ 0xC5, 0x12, /* Program RGB->YCrCb Color Space convertion matrix */
+ 0xC2, 0x4A, /* Program RGB->YCrCb Color Space convertion matrix */
+ 0xC6, 0x5E, /* Program RGB->YCrCb Color Space convertion matrix */
+ 0xBD, 0x19, /* Program RGB->YCrCb Color Space convertion matrix */
+ 0xBF, 0x42, /* Program RGB->YCrCb Color Space convertion matrix */
+ 0x8C, 0x1F, /* NTSC Subcarrier Frequency */
+ 0x8D, 0x7C, /* NTSC Subcarrier Frequency */
+ 0x8E, 0xF0, /* NTSC Subcarrier Frequency */
+ 0x8F, 0x21, /* NTSC Subcarrier Frequency */
+ 0x01, 0x00, /* SD-Only Mode */
+ 0x80, 0x30, /* SSAF Luma Filter Enabled, NTSC Mode */
+ 0x82, 0x8B, /* Step control on, pixel data invalid, pedestal on, PrPb SSAF on, CVBS/YC output */
+ 0x87, 0x80, /* SD Color Bar Test Pattern Enabled, DAC 2 = Luma, DAC 3 = Chroma */
+ 0x86, 0x82,
+ 0x8B, 0x11,
+ 0x88, 0x20,
+ 0x8A, 0x0d,
+};
+
+static const u8 init_PAL[] = {
+ 0x00, 0x1E, /* Power up all DACs and PLL */
+ 0xC3, 0x26, /* Program RGB->YCrCb Color Space convertion matrix */
+ 0xC5, 0x12, /* Program RGB->YCrCb Color Space convertion matrix */
+ 0xC2, 0x4A, /* Program RGB->YCrCb Color Space convertion matrix */
+ 0xC6, 0x5E, /* Program RGB->YCrCb Color Space convertion matrix */
+ 0xBD, 0x19, /* Program RGB->YCrCb Color Space convertion matrix */
+ 0xBF, 0x42, /* Program RGB->YCrCb Color Space convertion matrix */
+ 0x8C, 0xCB, /* PAL Subcarrier Frequency */
+ 0x8D, 0x8A, /* PAL Subcarrier Frequency */
+ 0x8E, 0x09, /* PAL Subcarrier Frequency */
+ 0x8F, 0x2A, /* PAL Subcarrier Frequency */
+ 0x01, 0x00, /* SD-Only Mode */
+ 0x80, 0x11, /* SSAF Luma Filter Enabled, PAL Mode */
+ 0x82, 0x8B, /* Step control on, pixel data invalid, pedestal on, PrPb SSAF on, CVBS/YC output */
+ 0x87, 0x80, /* SD Color Bar Test Pattern Enabled, DAC 2 = Luma, DAC 3 = Chroma */
+ 0x86, 0x82,
+ 0x8B, 0x11,
+ 0x88, 0x20,
+ 0x8A, 0x0d,
+};
+
+static const u8 init_NTSC_YCbCr[] = {
+ 0x00, 0x1E, /* Power up all DACs and PLL */
+ 0x8C, 0x1F, /* NTSC Subcarrier Frequency */
+ 0x8D, 0x7C, /* NTSC Subcarrier Frequency */
+ 0x8E, 0xF0, /* NTSC Subcarrier Frequency */
+ 0x8F, 0x21, /* NTSC Subcarrier Frequency */
+ 0x01, 0x00, /* SD-Only Mode */
+ 0x80, 0x30, /* SSAF Luma Filter Enabled, NTSC Mode */
+ 0x82, 0x8B, /* Step control on, pixel data invalid, pedestal on, PrPb SSAF on, CVBS/YC output */
+ 0x87, 0x00, /* DAC 2 = Luma, DAC 3 = Chroma */
+ 0x86, 0x82,
+ 0x8B, 0x11,
+ 0x88, 0x08,
+ 0x8A, 0x0d,
+};
+
+static const u8 init_PAL_YCbCr[] = {
+ 0x00, 0x1E, /* Power up all DACs and PLL */
+ 0x8C, 0xCB, /* PAL Subcarrier Frequency */
+ 0x8D, 0x8A, /* PAL Subcarrier Frequency */
+ 0x8E, 0x09, /* PAL Subcarrier Frequency */
+ 0x8F, 0x2A, /* PAL Subcarrier Frequency */
+ 0x01, 0x00, /* SD-Only Mode */
+ 0x80, 0x11, /* SSAF Luma Filter Enabled, PAL Mode */
+ 0x82, 0x8B, /* Step control on, pixel data invalid, pedestal on, PrPb SSAF on, CVBS/YC output */
+ 0x87, 0x00, /* DAC 2 = Luma, DAC 3 = Chroma */
+ 0x86, 0x82,
+ 0x8B, 0x11,
+ 0x88, 0x08,
+ 0x8A, 0x0d,
+};
+
+static struct adv7393fb_modes known_modes[] = {
+ /* NTSC 720x480 CRT */
+ {
+ .name = "NTSC 720x480",
+ .xres = 720,
+ .yres = 480,
+ .bpp = 16,
+ .vmode = FB_VMODE_INTERLACED,
+ .a_lines = 240,
+ .vb1_lines = 22,
+ .vb2_lines = 23,
+ .tot_lines = 525,
+ .boeft_blank = 16,
+ .aoeft_blank = 122,
+ .adv7393_i2c_initd = init_NTSC,
+ .adv7393_i2c_initd_len = sizeof(init_NTSC)
+ },
+ /* PAL 720x480 CRT */
+ {
+ .name = "PAL 720x576",
+ .xres = 720,
+ .yres = 576,
+ .bpp = 16,
+ .vmode = FB_VMODE_INTERLACED,
+ .a_lines = 288,
+ .vb1_lines = 24,
+ .vb2_lines = 25,
+ .tot_lines = 625,
+ .boeft_blank = 12,
+ .aoeft_blank = 132,
+ .adv7393_i2c_initd = init_PAL,
+ .adv7393_i2c_initd_len = sizeof(init_PAL)
+ },
+ /* NTSC 640x480 CRT Experimental */
+ {
+ .name = "NTSC 640x480",
+ .xres = 640,
+ .yres = 480,
+ .bpp = 16,
+ .vmode = FB_VMODE_INTERLACED,
+ .a_lines = 240,
+ .vb1_lines = 22,
+ .vb2_lines = 23,
+ .tot_lines = 525,
+ .boeft_blank = 16 + 40,
+ .aoeft_blank = 122 + 40,
+ .adv7393_i2c_initd = init_NTSC,
+ .adv7393_i2c_initd_len = sizeof(init_NTSC)
+ },
+ /* PAL 640x480 CRT Experimental */
+ {
+ .name = "PAL 640x480",
+ .xres = 640,
+ .yres = 480,
+ .bpp = 16,
+ .vmode = FB_VMODE_INTERLACED,
+ .a_lines = 288 - 20,
+ .vb1_lines = 24 + 20,
+ .vb2_lines = 25 + 20,
+ .tot_lines = 625,
+ .boeft_blank = 12 + 40,
+ .aoeft_blank = 132 + 40,
+ .adv7393_i2c_initd = init_PAL,
+ .adv7393_i2c_initd_len = sizeof(init_PAL)
+ },
+ /* NTSC 720x480 YCbCR */
+ {
+ .name = "NTSC 720x480 YCbCR",
+ .xres = 720,
+ .yres = 480,
+ .bpp = 16,
+ .vmode = FB_VMODE_INTERLACED,
+ .a_lines = 240,
+ .vb1_lines = 22,
+ .vb2_lines = 23,
+ .tot_lines = 525,
+ .boeft_blank = 16,
+ .aoeft_blank = 122,
+ .adv7393_i2c_initd = init_NTSC_YCbCr,
+ .adv7393_i2c_initd_len = sizeof(init_NTSC_YCbCr)
+ },
+ /* PAL 720x480 CRT */
+ {
+ .name = "PAL 720x576 YCbCR",
+ .xres = 720,
+ .yres = 576,
+ .bpp = 16,
+ .vmode = FB_VMODE_INTERLACED,
+ .a_lines = 288,
+ .vb1_lines = 24,
+ .vb2_lines = 25,
+ .tot_lines = 625,
+ .boeft_blank = 12,
+ .aoeft_blank = 132,
+ .adv7393_i2c_initd = init_PAL_YCbCr,
+ .adv7393_i2c_initd_len = sizeof(init_PAL_YCbCr)
+ }
+};
+
+struct adv7393fb_regs {
+
+};
+
+struct adv7393fb_device {
+ struct fb_info info; /* FB driver info record */
+
+ struct i2c_client *client;
+
+ struct dmasg *descriptor_list_head;
+ struct dmasg *vb1;
+ struct dmasg *av1;
+ struct dmasg *vb2;
+ struct dmasg *av2;
+
+ dma_addr_t dma_handle;
+
+ struct fb_info bfin_adv7393_fb;
+
+ struct adv7393fb_modes *modes;
+
+ struct adv7393fb_regs *regs; /* Registers memory map */
+ size_t regs_len;
+ size_t fb_len;
+ size_t line_len;
+ u16 open;
+ u16 *fb_mem; /* RGB Buffer */
+
+};
+
+#define to_adv7393fb_device(_info) \
+ (_info ? container_of(_info, struct adv7393fb_device, info) : NULL);
+
+static int bfin_adv7393_fb_open(struct fb_info *info, int user);
+static int bfin_adv7393_fb_release(struct fb_info *info, int user);
+static int bfin_adv7393_fb_check_var(struct fb_var_screeninfo *var,
+ struct fb_info *info);
+
+static int bfin_adv7393_fb_pan_display(struct fb_var_screeninfo *var,
+ struct fb_info *info);
+
+static int bfin_adv7393_fb_blank(int blank, struct fb_info *info);
+
+static void bfin_config_ppi(struct adv7393fb_device *fbdev);
+static int bfin_config_dma(struct adv7393fb_device *fbdev);
+static void bfin_disable_dma(void);
+static void bfin_enable_ppi(void);
+static void bfin_disable_ppi(void);
+
+static inline int adv7393_write(struct i2c_client *client, u8 reg, u8 value);
+static inline int adv7393_read(struct i2c_client *client, u8 reg);
+static int adv7393_write_block(struct i2c_client *client, const u8 *data,
+ unsigned int len);
+
+int bfin_adv7393_fb_cursor(struct fb_info *info, struct fb_cursor *cursor);
+static int bfin_adv7393_fb_setcolreg(u_int, u_int, u_int, u_int,
+ u_int, struct fb_info *info);
+
+#endif
DPRINTK("========================================\n");
}
+/**
+ * fb_edid_add_monspecs() - add monitor video modes from E-EDID data
+ * @edid: 128 byte array with an E-EDID block
+ * @spacs: monitor specs to be extended
+ */
+void fb_edid_add_monspecs(unsigned char *edid, struct fb_monspecs *specs)
+{
+ unsigned char *block;
+ struct fb_videomode *m;
+ int num = 0, i;
+ u8 svd[64], edt[(128 - 4) / DETAILED_TIMING_DESCRIPTION_SIZE];
+ u8 pos = 4, svd_n = 0;
+
+ if (!edid)
+ return;
+
+ if (!edid_checksum(edid))
+ return;
+
+ if (edid[0] != 0x2 ||
+ edid[2] < 4 || edid[2] > 128 - DETAILED_TIMING_DESCRIPTION_SIZE)
+ return;
+
+ DPRINTK(" Short Video Descriptors\n");
+
+ while (pos < edid[2]) {
+ u8 len = edid[pos] & 0x1f, type = (edid[pos] >> 5) & 7;
+ pr_debug("Data block %u of %u bytes\n", type, len);
+ if (type == 2)
+ for (i = pos; i < pos + len; i++) {
+ u8 idx = edid[pos + i] & 0x7f;
+ svd[svd_n++] = idx;
+ pr_debug("N%sative mode #%d\n",
+ edid[pos + i] & 0x80 ? "" : "on-n", idx);
+ }
+ pos += len + 1;
+ }
+
+ block = edid + edid[2];
+
+ DPRINTK(" Extended Detailed Timings\n");
+
+ for (i = 0; i < (128 - edid[2]) / DETAILED_TIMING_DESCRIPTION_SIZE;
+ i++, block += DETAILED_TIMING_DESCRIPTION_SIZE)
+ if (PIXEL_CLOCK)
+ edt[num++] = block - edid;
+
+ /* Yikes, EDID data is totally useless */
+ if (!(num + svd_n))
+ return;
+
+ m = kzalloc((specs->modedb_len + num + svd_n) *
+ sizeof(struct fb_videomode), GFP_KERNEL);
+
+ if (!m)
+ return;
+
+ memcpy(m, specs->modedb, specs->modedb_len * sizeof(struct fb_videomode));
+
+ for (i = specs->modedb_len; i < specs->modedb_len + num; i++) {
+ get_detailed_timing(edid + edt[i - specs->modedb_len], &m[i]);
+ if (i == specs->modedb_len)
+ m[i].flag |= FB_MODE_IS_FIRST;
+ pr_debug("Adding %ux%u@%u\n", m[i].xres, m[i].yres, m[i].refresh);
+ }
+
+ for (i = specs->modedb_len + num; i < specs->modedb_len + num + svd_n; i++) {
+ int idx = svd[i - specs->modedb_len - num];
+ if (!idx || idx > 63) {
+ pr_warning("Reserved SVD code %d\n", idx);
+ } else if (idx > ARRAY_SIZE(cea_modes) || !cea_modes[idx].xres) {
+ pr_warning("Unimplemented SVD code %d\n", idx);
+ } else {
+ memcpy(&m[i], cea_modes + idx, sizeof(m[i]));
+ pr_debug("Adding SVD #%d: %ux%u@%u\n", idx,
+ m[i].xres, m[i].yres, m[i].refresh);
+ }
+ }
+
+ kfree(specs->modedb);
+ specs->modedb = m;
+ specs->modedb_len = specs->modedb_len + num + svd_n;
+}
+
/*
* VESA Generalized Timing Formula (GTF)
*/
{
specs = NULL;
}
+void fb_edid_add_monspecs(unsigned char *edid, struct fb_monspecs *specs)
+{
+}
void fb_destroy_modedb(struct fb_videomode *modedb)
{
}
EXPORT_SYMBOL(fb_parse_edid);
EXPORT_SYMBOL(fb_edid_to_monspecs);
+EXPORT_SYMBOL(fb_edid_add_monspecs);
EXPORT_SYMBOL(fb_get_mode);
EXPORT_SYMBOL(fb_validate_mode);
EXPORT_SYMBOL(fb_destroy_modedb);
};
#ifdef CONFIG_FB_MODE_HELPERS
+const struct fb_videomode cea_modes[64] = {
+ /* #1: 640x480p@59.94/60Hz */
+ [1] = {
+ NULL, 60, 640, 480, 39722, 48, 16, 33, 10, 96, 2, 0, FB_VMODE_NONINTERLACED, 0,
+ },
+ /* #3: 720x480p@59.94/60Hz */
+ [3] = {
+ NULL, 60, 720, 480, 37037, 60, 16, 30, 9, 62, 6, 0, FB_VMODE_NONINTERLACED, 0,
+ },
+ /* #5: 1920x1080i@59.94/60Hz */
+ [5] = {
+ NULL, 60, 1920, 1080, 13763, 148, 88, 15, 2, 44, 5,
+ FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, FB_VMODE_INTERLACED, 0,
+ },
+ /* #7: 720(1440)x480iH@59.94/60Hz */
+ [7] = {
+ NULL, 60, 1440, 480, 18554/*37108*/, 114, 38, 15, 4, 124, 3, 0, FB_VMODE_INTERLACED, 0,
+ },
+ /* #9: 720(1440)x240pH@59.94/60Hz */
+ [9] = {
+ NULL, 60, 1440, 240, 18554, 114, 38, 16, 4, 124, 3, 0, FB_VMODE_NONINTERLACED, 0,
+ },
+ /* #18: 720x576pH@50Hz */
+ [18] = {
+ NULL, 50, 720, 576, 37037, 68, 12, 39, 5, 64, 5, 0, FB_VMODE_NONINTERLACED, 0,
+ },
+ /* #19: 1280x720p@50Hz */
+ [19] = {
+ NULL, 50, 1280, 720, 13468, 220, 440, 20, 5, 40, 5,
+ FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, FB_VMODE_NONINTERLACED, 0,
+ },
+ /* #20: 1920x1080i@50Hz */
+ [20] = {
+ NULL, 50, 1920, 1080, 13480, 148, 528, 15, 5, 528, 5,
+ FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, FB_VMODE_INTERLACED, 0,
+ },
+ /* #32: 1920x1080p@23.98/24Hz */
+ [32] = {
+ NULL, 24, 1920, 1080, 13468, 148, 638, 36, 4, 44, 5,
+ FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, FB_VMODE_NONINTERLACED, 0,
+ },
+ /* #35: (2880)x480p4x@59.94/60Hz */
+ [35] = {
+ NULL, 60, 2880, 480, 9250, 240, 64, 30, 9, 248, 6, 0, FB_VMODE_NONINTERLACED, 0,
+ },
+};
+
const struct fb_videomode vesa_modes[] = {
/* 0 640x350-85 VESA */
{ NULL, 85, 640, 350, 31746, 96, 32, 60, 32, 64, 3,
goto eremap;
}
- pr_debug("Remapped %x to %x at %p\n", sdc_reg->start, sdc_reg->end,
- mx3fb->reg_base);
+ pr_debug("Remapped %pR at %p\n", sdc_reg, mx3fb->reg_base);
/* IDMAC interface */
dmaengine_get();
functions to handle bitblt acceleration
************************************************************/
-/**
- * bltbit_wait_bitset - waits for change in register value
- * @info : framebuffer structure
- * @bit : value expected in register
- * @timeout : ...
- *
- * waits until value changes INTO bit
- */
-static u8
-bltbit_wait_bitset(struct fb_info *info, u8 bit, int timeout)
-{
- while (!(s1d13xxxfb_readreg(info->par, S1DREG_BBLT_CTL0) & bit)) {
- udelay(10);
- if (!--timeout) {
- dbg_blit("wait_bitset timeout\n");
- break;
- }
- }
-
- return timeout;
-}
-
/**
* bltbit_wait_bitclear - waits for change in register value
* @info : frambuffer structure
return timeout;
}
-/**
- * bltbit_fifo_status - checks the current status of the fifo
- * @info : framebuffer structure
- *
- * returns number of free words in buffer
- */
-static u8
-bltbit_fifo_status(struct fb_info *info)
-{
- u8 status;
-
- status = s1d13xxxfb_readreg(info->par, S1DREG_BBLT_CTL0);
-
- /* its empty so room for 16 words */
- if (status & BBLT_FIFO_EMPTY)
- return 16;
-
- /* its full so we dont want to add */
- if (status & BBLT_FIFO_FULL)
- return 0;
-
- /* its atleast half full but we can add one atleast */
- if (status & BBLT_FIFO_NOT_FULL)
- return 1;
-
- return 0;
-}
-
/*
* s1d13xxxfb_bitblt_copyarea - accelerated copyarea function
* @info : framebuffer structure
#include <linux/io.h>
#include <linux/uaccess.h>
#include <linux/interrupt.h>
+#include <linux/pm_runtime.h>
#include <mach/map.h>
#include <plat/regs-fb-v4.h>
return ret;
}
+static int s3c_fb_open(struct fb_info *info, int user)
+{
+ struct s3c_fb_win *win = info->par;
+ struct s3c_fb *sfb = win->parent;
+
+ pm_runtime_get_sync(sfb->dev);
+
+ return 0;
+}
+
+static int s3c_fb_release(struct fb_info *info, int user)
+{
+ struct s3c_fb_win *win = info->par;
+ struct s3c_fb *sfb = win->parent;
+
+ pm_runtime_put_sync(sfb->dev);
+
+ return 0;
+}
+
static struct fb_ops s3c_fb_ops = {
.owner = THIS_MODULE,
+ .fb_open = s3c_fb_open,
+ .fb_release = s3c_fb_release,
.fb_check_var = s3c_fb_check_var,
.fb_set_par = s3c_fb_set_par,
.fb_blank = s3c_fb_blank,
clk_enable(sfb->bus_clk);
+ pm_runtime_enable(sfb->dev);
+
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (!res) {
dev_err(dev, "failed to find registers\n");
dev_dbg(dev, "got resources (regs %p), probing windows\n", sfb->regs);
+ platform_set_drvdata(pdev, sfb);
+ pm_runtime_get_sync(sfb->dev);
+
/* setup gpio and output polarity controls */
pd->setup_gpio();
}
platform_set_drvdata(pdev, sfb);
+ pm_runtime_put_sync(sfb->dev);
return 0;
struct s3c_fb *sfb = platform_get_drvdata(pdev);
int win;
+ pm_runtime_get_sync(sfb->dev);
+
for (win = 0; win < S3C_FB_MAX_WIN; win++)
if (sfb->windows[win])
s3c_fb_release_win(sfb, sfb->windows[win]);
kfree(sfb);
+ pm_runtime_put_sync(sfb->dev);
+ pm_runtime_disable(sfb->dev);
+
return 0;
}
#ifdef CONFIG_PM
-static int s3c_fb_suspend(struct platform_device *pdev, pm_message_t state)
+static int s3c_fb_suspend(struct device *dev)
+{
+ struct platform_device *pdev = to_platform_device(dev);
+ struct s3c_fb *sfb = platform_get_drvdata(pdev);
+ struct s3c_fb_win *win;
+ int win_no;
+
+ for (win_no = S3C_FB_MAX_WIN - 1; win_no >= 0; win_no--) {
+ win = sfb->windows[win_no];
+ if (!win)
+ continue;
+
+ /* use the blank function to push into power-down */
+ s3c_fb_blank(FB_BLANK_POWERDOWN, win->fbinfo);
+ }
+
+ clk_disable(sfb->bus_clk);
+ return 0;
+}
+
+static int s3c_fb_resume(struct device *dev)
+{
+ struct platform_device *pdev = to_platform_device(dev);
+ struct s3c_fb *sfb = platform_get_drvdata(pdev);
+ struct s3c_fb_platdata *pd = sfb->pdata;
+ struct s3c_fb_win *win;
+ int win_no;
+
+ clk_enable(sfb->bus_clk);
+
+ /* setup registers */
+ writel(pd->vidcon1, sfb->regs + VIDCON1);
+
+ /* zero all windows before we do anything */
+ for (win_no = 0; win_no < sfb->variant.nr_windows; win_no++)
+ s3c_fb_clear_win(sfb, win_no);
+
+ for (win_no = 0; win_no < sfb->variant.nr_windows - 1; win_no++) {
+ void __iomem *regs = sfb->regs + sfb->variant.keycon;
+
+ regs += (win_no * 8);
+ writel(0xffffff, regs + WKEYCON0);
+ writel(0xffffff, regs + WKEYCON1);
+ }
+
+ /* restore framebuffers */
+ for (win_no = 0; win_no < S3C_FB_MAX_WIN; win_no++) {
+ win = sfb->windows[win_no];
+ if (!win)
+ continue;
+
+ dev_dbg(&pdev->dev, "resuming window %d\n", win_no);
+ s3c_fb_set_par(win->fbinfo);
+ }
+
+ return 0;
+}
+
+int s3c_fb_runtime_suspend(struct device *dev)
{
+ struct platform_device *pdev = to_platform_device(dev);
struct s3c_fb *sfb = platform_get_drvdata(pdev);
struct s3c_fb_win *win;
int win_no;
return 0;
}
-static int s3c_fb_resume(struct platform_device *pdev)
+int s3c_fb_runtime_resume(struct device *dev)
{
+ struct platform_device *pdev = to_platform_device(dev);
struct s3c_fb *sfb = platform_get_drvdata(pdev);
struct s3c_fb_platdata *pd = sfb->pdata;
struct s3c_fb_win *win;
return 0;
}
+
#else
#define s3c_fb_suspend NULL
#define s3c_fb_resume NULL
+#define s3c_fb_runtime_suspend NULL
+#define s3c_fb_runtime_resume NULL
#endif
};
MODULE_DEVICE_TABLE(platform, s3c_fb_driver_ids);
+static const struct dev_pm_ops s3cfb_pm_ops = {
+ .suspend = s3c_fb_suspend,
+ .resume = s3c_fb_resume,
+ .runtime_suspend = s3c_fb_runtime_suspend,
+ .runtime_resume = s3c_fb_runtime_resume,
+};
+
static struct platform_driver s3c_fb_driver = {
.probe = s3c_fb_probe,
.remove = __devexit_p(s3c_fb_remove),
- .suspend = s3c_fb_suspend,
- .resume = s3c_fb_resume,
.id_table = s3c_fb_driver_ids,
.driver = {
.name = "s3c-fb",
.owner = THIS_MODULE,
+ .pm = &s3cfb_pm_ops,
},
};
#include <video/sh_mipi_dsi.h>
#include <video/sh_mobile_lcdc.h>
-#define CMTSRTCTR 0x80d0
-#define CMTSRTREQ 0x8070
-
+#define SYSCTRL 0x0000
+#define SYSCONF 0x0004
+#define TIMSET 0x0008
+#define RESREQSET0 0x0018
+#define RESREQSET1 0x001c
+#define HSTTOVSET 0x0020
+#define LPRTOVSET 0x0024
+#define TATOVSET 0x0028
+#define PRTOVSET 0x002c
+#define DSICTRL 0x0030
#define DSIINTE 0x0060
+#define PHYCTRL 0x0070
+
+/* relative to linkbase */
+#define DTCTR 0x0000
+#define VMCTR1 0x0020
+#define VMCTR2 0x0024
+#define VMLEN1 0x0028
+#define CMTSRTREQ 0x0070
+#define CMTSRTCTR 0x00d0
/* E.g., sh7372 has 2 MIPI-DSIs - one for each LCDC */
#define MAX_SH_MIPI_DSI 2
struct sh_mipi {
void __iomem *base;
+ void __iomem *linkbase;
struct clk *dsit_clk;
struct clk *dsip_clk;
+ void *next_board_data;
+ void (*next_display_on)(void *board_data, struct fb_info *info);
+ void (*next_display_off)(void *board_data);
};
static struct sh_mipi *mipi_dsi[MAX_SH_MIPI_DSI];
int cnt = 100;
/* transmit a short packet to LCD panel */
- iowrite32(1 | data, mipi->base + 0x80d0); /* CMTSRTCTR */
- iowrite32(1, mipi->base + 0x8070); /* CMTSRTREQ */
+ iowrite32(1 | data, mipi->linkbase + CMTSRTCTR);
+ iowrite32(1, mipi->linkbase + CMTSRTREQ);
- while ((ioread32(mipi->base + 0x8070) & 1) && --cnt)
+ while ((ioread32(mipi->linkbase + CMTSRTREQ) & 1) && --cnt)
udelay(1);
return cnt ? 0 : -ETIMEDOUT;
* enable LCDC data tx, transition to LPS after completion of each HS
* packet
*/
- iowrite32(0x00000002 | enable, mipi->base + 0x8000); /* DTCTR */
+ iowrite32(0x00000002 | enable, mipi->linkbase + DTCTR);
}
static void sh_mipi_shutdown(struct platform_device *pdev)
struct sh_mipi *mipi = arg;
sh_mipi_dsi_enable(mipi, true);
+
+ if (mipi->next_display_on)
+ mipi->next_display_on(mipi->next_board_data, info);
}
static void mipi_display_off(void *arg)
{
struct sh_mipi *mipi = arg;
+ if (mipi->next_display_off)
+ mipi->next_display_off(mipi->next_board_data);
+
sh_mipi_dsi_enable(mipi, false);
}
return -EINVAL;
/* reset DSI link */
- iowrite32(0x00000001, base); /* SYSCTRL */
+ iowrite32(0x00000001, base + SYSCTRL);
/* Hold reset for 100 cycles of the slowest of bus, HS byte and LP clock */
udelay(50);
- iowrite32(0x00000000, base); /* SYSCTRL */
+ iowrite32(0x00000000, base + SYSCTRL);
/* setup DSI link */
* ECC check enable
* additionally enable first two lanes
*/
- iowrite32(0x00003703, base + 0x04); /* SYSCONF */
+ iowrite32(0x00003703, base + SYSCONF);
/*
* T_wakeup = 0x7000
* T_hs-trail = 3
* T_clk-trail = 3
* T_clk-prepare = 2
*/
- iowrite32(0x70003332, base + 0x08); /* TIMSET */
+ iowrite32(0x70003332, base + TIMSET);
/* no responses requested */
- iowrite32(0x00000000, base + 0x18); /* RESREQSET0 */
+ iowrite32(0x00000000, base + RESREQSET0);
/* request response to packets of type 0x28 */
- iowrite32(0x00000100, base + 0x1c); /* RESREQSET1 */
+ iowrite32(0x00000100, base + RESREQSET1);
/* High-speed transmission timeout, default 0xffffffff */
- iowrite32(0x0fffffff, base + 0x20); /* HSTTOVSET */
+ iowrite32(0x0fffffff, base + HSTTOVSET);
/* LP reception timeout, default 0xffffffff */
- iowrite32(0x0fffffff, base + 0x24); /* LPRTOVSET */
+ iowrite32(0x0fffffff, base + LPRTOVSET);
/* Turn-around timeout, default 0xffffffff */
- iowrite32(0x0fffffff, base + 0x28); /* TATOVSET */
+ iowrite32(0x0fffffff, base + TATOVSET);
/* Peripheral reset timeout, default 0xffffffff */
- iowrite32(0x0fffffff, base + 0x2c); /* PRTOVSET */
+ iowrite32(0x0fffffff, base + PRTOVSET);
/* Enable timeout counters */
- iowrite32(0x00000f00, base + 0x30); /* DSICTRL */
+ iowrite32(0x00000f00, base + DSICTRL);
/* Interrupts not used, disable all */
iowrite32(0, base + DSIINTE);
/* DSI-Tx bias on */
- iowrite32(0x00000001, base + 0x70); /* PHYCTRL */
+ iowrite32(0x00000001, base + PHYCTRL);
udelay(200);
/* Deassert resets, power on, set multiplier */
- iowrite32(0x03070b01, base + 0x70); /* PHYCTRL */
+ iowrite32(0x03070b01, base + PHYCTRL);
/* setup l-bridge */
* Enable transmission of all packets,
* transmit LPS after each HS packet completion
*/
- iowrite32(0x00000006, base + 0x8000); /* DTCTR */
+ iowrite32(0x00000006, mipi->linkbase + DTCTR);
/* VSYNC width = 2 (<< 17) */
- iowrite32(0x00040000 | (pctype << 12) | datatype, base + 0x8020); /* VMCTR1 */
+ iowrite32(0x00040000 | (pctype << 12) | datatype,
+ mipi->linkbase + VMCTR1);
/*
* Non-burst mode with sync pulses: VSE and HSE are output,
* HSA period allowed, no commands in LP
*/
- iowrite32(0x00e00000, base + 0x8024); /* VMCTR2 */
+ iowrite32(0x00e00000, mipi->linkbase + VMCTR2);
/*
* 0x660 = 1632 bytes per line (RGB24, 544 pixels: see
* sh_mobile_lcdc_info.ch[0].lcd_cfg[0].xres), HSALEN = 1 - default
* (unused, since VMCTR2[HSABM] = 0)
*/
- iowrite32(1 | (linelength << 16), base + 0x8028); /* VMLEN1 */
+ iowrite32(1 | (linelength << 16), mipi->linkbase + VMLEN1);
msleep(5);
struct sh_mipi *mipi;
struct sh_mipi_dsi_info *pdata = pdev->dev.platform_data;
struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ struct resource *res2 = platform_get_resource(pdev, IORESOURCE_MEM, 1);
unsigned long rate, f_current;
int idx = pdev->id, ret;
char dsip_clk[] = "dsi.p_clk";
- if (!res || idx >= ARRAY_SIZE(mipi_dsi) || !pdata)
+ if (!res || !res2 || idx >= ARRAY_SIZE(mipi_dsi) || !pdata)
return -ENODEV;
mutex_lock(&array_lock);
goto emap;
}
+ if (!request_mem_region(res2->start, resource_size(res2), pdev->name)) {
+ dev_err(&pdev->dev, "MIPI register region 2 already claimed\n");
+ ret = -EBUSY;
+ goto ereqreg2;
+ }
+
+ mipi->linkbase = ioremap(res2->start, resource_size(res2));
+ if (!mipi->linkbase) {
+ ret = -ENOMEM;
+ goto emap2;
+ }
+
mipi->dsit_clk = clk_get(&pdev->dev, "dsit_clk");
if (IS_ERR(mipi->dsit_clk)) {
ret = PTR_ERR(mipi->dsit_clk);
mutex_unlock(&array_lock);
platform_set_drvdata(pdev, mipi);
+ /* Save original LCDC callbacks */
+ mipi->next_board_data = pdata->lcd_chan->board_cfg.board_data;
+ mipi->next_display_on = pdata->lcd_chan->board_cfg.display_on;
+ mipi->next_display_off = pdata->lcd_chan->board_cfg.display_off;
+
/* Set up LCDC callbacks */
pdata->lcd_chan->board_cfg.board_data = mipi;
pdata->lcd_chan->board_cfg.display_on = mipi_display_on;
esettrate:
clk_put(mipi->dsit_clk);
eclktget:
+ iounmap(mipi->linkbase);
+emap2:
+ release_mem_region(res2->start, resource_size(res2));
+ereqreg2:
iounmap(mipi->base);
emap:
release_mem_region(res->start, resource_size(res));
{
struct sh_mipi_dsi_info *pdata = pdev->dev.platform_data;
struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ struct resource *res2 = platform_get_resource(pdev, IORESOURCE_MEM, 1);
struct sh_mipi *mipi = platform_get_drvdata(pdev);
int i, ret;
clk_disable(mipi->dsit_clk);
clk_put(mipi->dsit_clk);
clk_put(mipi->dsip_clk);
+ iounmap(mipi->linkbase);
+ if (res2)
+ release_mem_region(res2->start, resource_size(res2));
iounmap(mipi->base);
if (res)
release_mem_region(res->start, resource_size(res));
struct sh_hdmi {
void __iomem *base;
enum hotplug_state hp_state; /* hot-plug status */
- bool preprogrammed_mode; /* use a pre-programmed VIC or the external mode */
+ u8 preprogrammed_vic; /* use a pre-programmed VIC or
+ the external mode */
+ u8 edid_block_addr;
+ u8 edid_segment_nr;
+ u8 edid_blocks;
struct clk *hdmi_clk;
struct device *dev;
struct fb_info *info;
hdmi_write(hdmi, var->vsync_len, HDMI_EXTERNAL_V_DURATION);
/* Set bit 0 of HDMI_EXTERNAL_VIDEO_PARAM_SETTINGS here for external mode */
- if (!hdmi->preprogrammed_mode)
+ if (!hdmi->preprogrammed_vic)
hdmi_write(hdmi, sync | 1 | (voffset << 4),
HDMI_EXTERNAL_VIDEO_PARAM_SETTINGS);
}
*/
static void sh_hdmi_phy_config(struct sh_hdmi *hdmi)
{
- if (hdmi->var.yres > 480) {
+ if (hdmi->var.pixclock < 10000) {
+ /* for 1080p8bit 148MHz */
+ hdmi_write(hdmi, 0x1d, HDMI_SLIPHDMIT_PARAM_SETTINGS_1);
+ hdmi_write(hdmi, 0x00, HDMI_SLIPHDMIT_PARAM_SETTINGS_2);
+ hdmi_write(hdmi, 0x00, HDMI_SLIPHDMIT_PARAM_SETTINGS_3);
+ hdmi_write(hdmi, 0x4c, HDMI_SLIPHDMIT_PARAM_SETTINGS_5);
+ hdmi_write(hdmi, 0x1e, HDMI_SLIPHDMIT_PARAM_SETTINGS_6);
+ hdmi_write(hdmi, 0x48, HDMI_SLIPHDMIT_PARAM_SETTINGS_7);
+ hdmi_write(hdmi, 0x0e, HDMI_SLIPHDMIT_PARAM_SETTINGS_8);
+ hdmi_write(hdmi, 0x25, HDMI_SLIPHDMIT_PARAM_SETTINGS_9);
+ hdmi_write(hdmi, 0x04, HDMI_SLIPHDMIT_PARAM_SETTINGS_10);
+ } else if (hdmi->var.pixclock < 30000) {
/* 720p, 8bit, 74.25MHz. Might need to be adjusted for other formats */
/*
* [1:0] Speed_A
hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB3);
/*
- * VIC = 1280 x 720p: ignored if external config is used
- * Send 2 for 720 x 480p, 16 for 1080p, ignored in external mode
+ * VIC should be ignored if external config is used, so, we could just use 0,
+ * but play safe and use a valid value in any case just in case
*/
- if (hdmi->var.yres == 1080 && hdmi->var.xres == 1920)
- vic = 16;
- else if (hdmi->var.yres == 480 && hdmi->var.xres == 720)
- vic = 2;
+ if (hdmi->preprogrammed_vic)
+ vic = hdmi->preprogrammed_vic;
else
vic = 4;
hdmi_write(hdmi, vic, HDMI_CTRL_PKT_BUF_ACCESS_PB4);
}
static unsigned long sh_hdmi_rate_error(struct sh_hdmi *hdmi,
- const struct fb_videomode *mode)
+ const struct fb_videomode *mode,
+ unsigned long *hdmi_rate, unsigned long *parent_rate)
{
- long target = PICOS2KHZ(mode->pixclock) * 1000,
- rate = clk_round_rate(hdmi->hdmi_clk, target);
- unsigned long rate_error = rate > 0 ? abs(rate - target) : ULONG_MAX;
+ unsigned long target = PICOS2KHZ(mode->pixclock) * 1000, rate_error;
+ struct sh_mobile_hdmi_info *pdata = hdmi->dev->platform_data;
+
+ *hdmi_rate = clk_round_rate(hdmi->hdmi_clk, target);
+ if ((long)*hdmi_rate < 0)
+ *hdmi_rate = clk_get_rate(hdmi->hdmi_clk);
+
+ rate_error = (long)*hdmi_rate > 0 ? abs(*hdmi_rate - target) : ULONG_MAX;
+ if (rate_error && pdata->clk_optimize_parent)
+ rate_error = pdata->clk_optimize_parent(target, hdmi_rate, parent_rate);
+ else if (clk_get_parent(hdmi->hdmi_clk))
+ *parent_rate = clk_get_rate(clk_get_parent(hdmi->hdmi_clk));
dev_dbg(hdmi->dev, "%u-%u-%u-%u x %u-%u-%u-%u\n",
mode->left_margin, mode->xres,
mode->upper_margin, mode->yres,
mode->lower_margin, mode->vsync_len);
- dev_dbg(hdmi->dev, "\t@%lu(+/-%lu)Hz, e=%lu / 1000, r=%uHz\n", target,
- rate_error, rate_error ? 10000 / (10 * target / rate_error) : 0,
- mode->refresh);
+ dev_dbg(hdmi->dev, "\t@%lu(+/-%lu)Hz, e=%lu / 1000, r=%uHz, p=%luHz\n", target,
+ rate_error, rate_error ? 10000 / (10 * target / rate_error) : 0,
+ mode->refresh, *parent_rate);
return rate_error;
}
-static int sh_hdmi_read_edid(struct sh_hdmi *hdmi)
+static int sh_hdmi_read_edid(struct sh_hdmi *hdmi, unsigned long *hdmi_rate,
+ unsigned long *parent_rate)
{
struct fb_var_screeninfo tmpvar;
struct fb_var_screeninfo *var = &tmpvar;
printk(KERN_CONT "\n");
#endif
- fb_edid_to_monspecs(edid, &hdmi->monspec);
+ if (!hdmi->edid_blocks) {
+ fb_edid_to_monspecs(edid, &hdmi->monspec);
+ hdmi->edid_blocks = edid[126] + 1;
+
+ dev_dbg(hdmi->dev, "%d main modes, %d extension blocks\n",
+ hdmi->monspec.modedb_len, hdmi->edid_blocks - 1);
+ } else {
+ dev_dbg(hdmi->dev, "Extension %u detected, DTD start %u\n",
+ edid[0], edid[2]);
+ fb_edid_add_monspecs(edid, &hdmi->monspec);
+ }
+
+ if (hdmi->edid_blocks > hdmi->edid_segment_nr * 2 +
+ (hdmi->edid_block_addr >> 7) + 1) {
+ /* More blocks to read */
+ if (hdmi->edid_block_addr) {
+ hdmi->edid_block_addr = 0;
+ hdmi->edid_segment_nr++;
+ } else {
+ hdmi->edid_block_addr = 0x80;
+ }
+ /* Set EDID word address */
+ hdmi_write(hdmi, hdmi->edid_block_addr, HDMI_EDID_WORD_ADDRESS);
+ /* Enable EDID interrupt */
+ hdmi_write(hdmi, 0xC6, HDMI_INTERRUPT_MASK_1);
+ /* Set EDID segment pointer - starts reading EDID */
+ hdmi_write(hdmi, hdmi->edid_segment_nr, HDMI_EDID_SEGMENT_POINTER);
+ return -EAGAIN;
+ }
+
+ /* All E-EDID blocks ready */
+ dev_dbg(hdmi->dev, "%d main and extended modes\n", hdmi->monspec.modedb_len);
fb_get_options("sh_mobile_lcdc", &forced);
if (forced && *forced) {
for (i = 0, mode = hdmi->monspec.modedb;
f_width && f_height && i < hdmi->monspec.modedb_len && !exact_match;
i++, mode++) {
- unsigned long rate_error = sh_hdmi_rate_error(hdmi, mode);
+ unsigned long rate_error;
/* No interest in unmatching modes */
if (f_width != mode->xres || f_height != mode->yres)
continue;
+
+ rate_error = sh_hdmi_rate_error(hdmi, mode, hdmi_rate, parent_rate);
+
if (f_refresh == mode->refresh || (!f_refresh && !rate_error))
/*
* Exact match if either the refresh rate matches or it
if (modelist) {
found = &modelist->mode;
- found_rate_error = sh_hdmi_rate_error(hdmi, found);
+ found_rate_error = sh_hdmi_rate_error(hdmi, found, hdmi_rate, parent_rate);
}
}
if (!found)
return -ENXIO;
- dev_info(hdmi->dev, "Using %s mode %ux%u@%uHz (%luHz), clock error %luHz\n",
- modelist ? "default" : "EDID", found->xres, found->yres,
- found->refresh, PICOS2KHZ(found->pixclock) * 1000, found_rate_error);
-
- if ((found->xres == 720 && found->yres == 480) ||
- (found->xres == 1280 && found->yres == 720) ||
- (found->xres == 1920 && found->yres == 1080))
- hdmi->preprogrammed_mode = true;
+ if (found->xres == 640 && found->yres == 480 && found->refresh == 60)
+ hdmi->preprogrammed_vic = 1;
+ else if (found->xres == 720 && found->yres == 480 && found->refresh == 60)
+ hdmi->preprogrammed_vic = 2;
+ else if (found->xres == 720 && found->yres == 576 && found->refresh == 50)
+ hdmi->preprogrammed_vic = 17;
+ else if (found->xres == 1280 && found->yres == 720 && found->refresh == 60)
+ hdmi->preprogrammed_vic = 4;
+ else if (found->xres == 1920 && found->yres == 1080 && found->refresh == 24)
+ hdmi->preprogrammed_vic = 32;
+ else if (found->xres == 1920 && found->yres == 1080 && found->refresh == 50)
+ hdmi->preprogrammed_vic = 31;
+ else if (found->xres == 1920 && found->yres == 1080 && found->refresh == 60)
+ hdmi->preprogrammed_vic = 16;
else
- hdmi->preprogrammed_mode = false;
+ hdmi->preprogrammed_vic = 0;
+
+ dev_dbg(hdmi->dev, "Using %s %s mode %ux%u@%uHz (%luHz), clock error %luHz\n",
+ modelist ? "default" : "EDID", hdmi->preprogrammed_vic ? "VIC" : "external",
+ found->xres, found->yres, found->refresh,
+ PICOS2KHZ(found->pixclock) * 1000, found_rate_error);
fb_videomode_to_var(&hdmi->var, found);
sh_hdmi_external_video_param(hdmi);
/* Check, if hot plug & MSENS pin status are both high */
if ((msens & 0xC0) == 0xC0) {
/* Display plug in */
+ hdmi->edid_segment_nr = 0;
+ hdmi->edid_block_addr = 0;
+ hdmi->edid_blocks = 0;
hdmi->hp_state = HDMI_HOTPLUG_CONNECTED;
/* Set EDID word address */
hdmi_write(hdmi, 0x00, HDMI_EDID_WORD_ADDRESS);
- /* Set EDID segment pointer */
- hdmi_write(hdmi, 0x00, HDMI_EDID_SEGMENT_POINTER);
/* Enable EDID interrupt */
hdmi_write(hdmi, 0xC6, HDMI_INTERRUPT_MASK_1);
+ /* Set EDID segment pointer - starts reading EDID */
+ hdmi_write(hdmi, 0x00, HDMI_EDID_SEGMENT_POINTER);
} else if (!(status1 & 0x80)) {
/* Display unplug, beware multiple interrupts */
- if (hdmi->hp_state != HDMI_HOTPLUG_DISCONNECTED)
+ if (hdmi->hp_state != HDMI_HOTPLUG_DISCONNECTED) {
+ hdmi->hp_state = HDMI_HOTPLUG_DISCONNECTED;
schedule_delayed_work(&hdmi->edid_work, 0);
-
- hdmi->hp_state = HDMI_HOTPLUG_DISCONNECTED;
+ }
/* display_off will switch back to mode_a */
}
} else if (status1 & 2) {
/* EDID error interrupt: retry */
/* Set EDID word address */
- hdmi_write(hdmi, 0x00, HDMI_EDID_WORD_ADDRESS);
+ hdmi_write(hdmi, hdmi->edid_block_addr, HDMI_EDID_WORD_ADDRESS);
/* Set EDID segment pointer */
- hdmi_write(hdmi, 0x00, HDMI_EDID_SEGMENT_POINTER);
+ hdmi_write(hdmi, hdmi->edid_segment_nr, HDMI_EDID_SEGMENT_POINTER);
} else if (status1 & 4) {
/* Disable EDID interrupt */
hdmi_write(hdmi, 0xC0, HDMI_INTERRUPT_MASK_1);
- hdmi->hp_state = HDMI_HOTPLUG_EDID_DONE;
schedule_delayed_work(&hdmi->edid_work, msecs_to_jiffies(10));
}
/**
* sh_hdmi_clk_configure() - set HDMI clock frequency and enable the clock
- * @hdmi: driver context
- * @pixclock: pixel clock period in picoseconds
- * return: configured positive rate if successful
- * 0 if couldn't set the rate, but managed to enable the clock
- * negative error, if couldn't enable the clock
+ * @hdmi: driver context
+ * @hdmi_rate: HDMI clock frequency in Hz
+ * @parent_rate: if != 0 - set parent clock rate for optimal precision
+ * return: configured positive rate if successful
+ * 0 if couldn't set the rate, but managed to enable the
+ * clock, negative error, if couldn't enable the clock
*/
-static long sh_hdmi_clk_configure(struct sh_hdmi *hdmi, unsigned long pixclock)
+static long sh_hdmi_clk_configure(struct sh_hdmi *hdmi, unsigned long hdmi_rate,
+ unsigned long parent_rate)
{
- long rate;
int ret;
- rate = PICOS2KHZ(pixclock) * 1000;
- rate = clk_round_rate(hdmi->hdmi_clk, rate);
- if (rate > 0) {
- ret = clk_set_rate(hdmi->hdmi_clk, rate);
+ if (parent_rate && clk_get_parent(hdmi->hdmi_clk)) {
+ ret = clk_set_rate(clk_get_parent(hdmi->hdmi_clk), parent_rate);
if (ret < 0) {
- dev_warn(hdmi->dev, "Cannot set rate %ld: %d\n", rate, ret);
- rate = 0;
+ dev_warn(hdmi->dev, "Cannot set parent rate %ld: %d\n", parent_rate, ret);
+ hdmi_rate = clk_round_rate(hdmi->hdmi_clk, hdmi_rate);
} else {
- dev_dbg(hdmi->dev, "HDMI set frequency %lu\n", rate);
+ dev_dbg(hdmi->dev, "HDMI set parent frequency %lu\n", parent_rate);
}
- } else {
- rate = 0;
- dev_warn(hdmi->dev, "Cannot get suitable rate: %ld\n", rate);
}
- ret = clk_enable(hdmi->hdmi_clk);
+ ret = clk_set_rate(hdmi->hdmi_clk, hdmi_rate);
if (ret < 0) {
- dev_err(hdmi->dev, "Cannot enable clock: %d\n", ret);
- return ret;
+ dev_warn(hdmi->dev, "Cannot set rate %ld: %d\n", hdmi_rate, ret);
+ hdmi_rate = 0;
+ } else {
+ dev_dbg(hdmi->dev, "HDMI set frequency %lu\n", hdmi_rate);
}
- return rate;
+ return hdmi_rate;
}
/* Hotplug interrupt occurred, read EDID */
mutex_lock(&hdmi->mutex);
- if (hdmi->hp_state == HDMI_HOTPLUG_EDID_DONE) {
+ if (hdmi->hp_state == HDMI_HOTPLUG_CONNECTED) {
+ unsigned long parent_rate = 0, hdmi_rate;
+
/* A device has been plugged in */
pm_runtime_get_sync(hdmi->dev);
- ret = sh_hdmi_read_edid(hdmi);
+ ret = sh_hdmi_read_edid(hdmi, &hdmi_rate, &parent_rate);
if (ret < 0)
goto out;
+ hdmi->hp_state = HDMI_HOTPLUG_EDID_DONE;
+
/* Reconfigure the clock */
- clk_disable(hdmi->hdmi_clk);
- ret = sh_hdmi_clk_configure(hdmi, hdmi->var.pixclock);
+ ret = sh_hdmi_clk_configure(hdmi, hdmi_rate, parent_rate);
if (ret < 0)
goto out;
}
out:
- if (ret < 0)
+ if (ret < 0 && ret != -EAGAIN)
hdmi->hp_state = HDMI_HOTPLUG_DISCONNECTED;
mutex_unlock(&hdmi->mutex);
goto egetclk;
}
- /* Some arbitrary relaxed pixclock just to get things started */
- rate = sh_hdmi_clk_configure(hdmi, 37037);
+ /* An arbitrary relaxed pixclock just to get things started: from standard 480p */
+ rate = clk_round_rate(hdmi->hdmi_clk, PICOS2KHZ(37037));
+ if (rate > 0)
+ rate = sh_hdmi_clk_configure(hdmi, rate, 0);
+
if (rate < 0) {
ret = rate;
goto erate;
}
+ ret = clk_enable(hdmi->hdmi_clk);
+ if (ret < 0) {
+ dev_err(hdmi->dev, "Cannot enable clock: %d\n", ret);
+ goto erate;
+ }
+
dev_dbg(&pdev->dev, "Enabled HDMI clock at %luHz\n", rate);
if (!request_mem_region(res->start, resource_size(res), dev_name(&pdev->dev))) {
platform_set_drvdata(pdev, hdmi);
- /* Product and revision IDs are 0 in sh-mobile version */
- dev_info(&pdev->dev, "Detected HDMI controller 0x%x:0x%x\n",
- hdmi_read(hdmi, HDMI_PRODUCT_ID), hdmi_read(hdmi, HDMI_REVISION_ID));
-
/* Set up LCDC callbacks */
board_cfg = &pdata->lcd_chan->board_cfg;
board_cfg->owner = THIS_MODULE;
pm_runtime_enable(&pdev->dev);
pm_runtime_resume(&pdev->dev);
+ /* Product and revision IDs are 0 in sh-mobile version */
+ dev_info(&pdev->dev, "Detected HDMI controller 0x%x:0x%x\n",
+ hdmi_read(hdmi, HDMI_PRODUCT_ID), hdmi_read(hdmi, HDMI_REVISION_ID));
+
ret = request_irq(irq, sh_hdmi_hotplug, 0,
dev_name(&pdev->dev), hdmi);
if (ret < 0) {
};
#define NR_SHARED_REGS ARRAY_SIZE(lcdc_shared_regs)
-#define DEFAULT_XRES 1280
-#define DEFAULT_YRES 1024
+#define MAX_XRES 1920
+#define MAX_YRES 1080
static unsigned long lcdc_offs_mainlcd[NR_CH_REGS] = {
[LDDCKPAT1R] = 0x400,
{
struct sh_mobile_lcdc_chan *ch = info->par;
- if (var->xres < 160 || var->xres > 1920 ||
- var->yres < 120 || var->yres > 1080 ||
- var->left_margin < 32 || var->left_margin > 320 ||
- var->right_margin < 12 || var->right_margin > 240 ||
- var->upper_margin < 12 || var->upper_margin > 120 ||
- var->lower_margin < 1 || var->lower_margin > 64 ||
- var->hsync_len < 32 || var->hsync_len > 240 ||
- var->vsync_len < 2 || var->vsync_len > 64 ||
- var->pixclock < 6000 || var->pixclock > 40000 ||
+ if (var->xres > MAX_XRES || var->yres > MAX_YRES ||
var->xres * var->yres * (ch->cfg.bpp / 8) * 2 > info->fix.smem_len) {
- dev_warn(info->dev, "Invalid info: %u %u %u %u %u %u %u %u %u!\n",
- var->xres, var->yres,
- var->left_margin, var->right_margin,
- var->upper_margin, var->lower_margin,
- var->hsync_len, var->vsync_len,
- var->pixclock);
+ dev_warn(info->dev, "Invalid info: %u-%u-%u-%u x %u-%u-%u-%u @ %lukHz!\n",
+ var->left_margin, var->xres, var->right_margin, var->hsync_len,
+ var->upper_margin, var->yres, var->lower_margin, var->vsync_len,
+ PICOS2KHZ(var->pixclock));
return -EINVAL;
}
return 0;
}
if (!mode)
- max_size = DEFAULT_XRES * DEFAULT_YRES;
+ max_size = MAX_XRES * MAX_YRES;
else if (max_cfg)
dev_dbg(&pdev->dev, "Found largest videomode %ux%u\n",
max_cfg->xres, max_cfg->yres);
#include <linux/module.h>
#include <linux/interrupt.h>
#include <linux/platform_device.h>
+#include <linux/list.h>
+#include <linux/pm.h>
+#include <asm/olpc.h>
/*
* The default port config.
{ 0, 0, 0, 0 }
};
+/*
+ * The OLPC XO-1.5 puts the camera power and reset lines onto
+ * GPIO 2C.
+ */
+static const struct via_port_cfg olpc_adap_configs[] = {
+ [VIA_PORT_26] = { VIA_PORT_I2C, VIA_MODE_I2C, VIASR, 0x26 },
+ [VIA_PORT_31] = { VIA_PORT_I2C, VIA_MODE_I2C, VIASR, 0x31 },
+ [VIA_PORT_25] = { VIA_PORT_GPIO, VIA_MODE_GPIO, VIASR, 0x25 },
+ [VIA_PORT_2C] = { VIA_PORT_GPIO, VIA_MODE_GPIO, VIASR, 0x2c },
+ [VIA_PORT_3D] = { VIA_PORT_GPIO, VIA_MODE_GPIO, VIASR, 0x3d },
+ { 0, 0, 0, 0 }
+};
+
/*
* We currently only support one viafb device (will there ever be
* more than one?), so just declare it globally here.
}
}
+/*
+ * Power management functions
+ */
+#ifdef CONFIG_PM
+static LIST_HEAD(viafb_pm_hooks);
+static DEFINE_MUTEX(viafb_pm_hooks_lock);
+
+void viafb_pm_register(struct viafb_pm_hooks *hooks)
+{
+ INIT_LIST_HEAD(&hooks->list);
+
+ mutex_lock(&viafb_pm_hooks_lock);
+ list_add_tail(&hooks->list, &viafb_pm_hooks);
+ mutex_unlock(&viafb_pm_hooks_lock);
+}
+EXPORT_SYMBOL_GPL(viafb_pm_register);
+
+void viafb_pm_unregister(struct viafb_pm_hooks *hooks)
+{
+ mutex_lock(&viafb_pm_hooks_lock);
+ list_del(&hooks->list);
+ mutex_unlock(&viafb_pm_hooks_lock);
+}
+EXPORT_SYMBOL_GPL(viafb_pm_unregister);
+
+static int via_suspend(struct pci_dev *pdev, pm_message_t state)
+{
+ struct viafb_pm_hooks *hooks;
+
+ if (state.event != PM_EVENT_SUSPEND)
+ return 0;
+ /*
+ * "I've occasionally hit a few drivers that caused suspend
+ * failures, and each and every time it was a driver bug, and
+ * the right thing to do was to just ignore the error and suspend
+ * anyway - returning an error code and trying to undo the suspend
+ * is not what anybody ever really wants, even if our model
+ *_allows_ for it."
+ * -- Linus Torvalds, Dec. 7, 2009
+ */
+ mutex_lock(&viafb_pm_hooks_lock);
+ list_for_each_entry_reverse(hooks, &viafb_pm_hooks, list)
+ hooks->suspend(hooks->private);
+ mutex_unlock(&viafb_pm_hooks_lock);
+
+ pci_save_state(pdev);
+ pci_disable_device(pdev);
+ pci_set_power_state(pdev, pci_choose_state(pdev, state));
+ return 0;
+}
+
+static int via_resume(struct pci_dev *pdev)
+{
+ struct viafb_pm_hooks *hooks;
+
+ /* Get the bus side powered up */
+ pci_set_power_state(pdev, PCI_D0);
+ pci_restore_state(pdev);
+ if (pci_enable_device(pdev))
+ return 0;
+
+ pci_set_master(pdev);
+
+ /* Now bring back any subdevs */
+ mutex_lock(&viafb_pm_hooks_lock);
+ list_for_each_entry(hooks, &viafb_pm_hooks, list)
+ hooks->resume(hooks->private);
+ mutex_unlock(&viafb_pm_hooks_lock);
+
+ return 0;
+}
+#endif /* CONFIG_PM */
static int __devinit via_pci_probe(struct pci_dev *pdev,
const struct pci_device_id *ent)
ret = pci_enable_device(pdev);
if (ret)
return ret;
+
/*
* Global device initialization.
*/
global_dev.pdev = pdev;
global_dev.chip_type = ent->driver_data;
global_dev.port_cfg = adap_configs;
+ if (machine_is_olpc())
+ global_dev.port_cfg = olpc_adap_configs;
+
spin_lock_init(&global_dev.reg_lock);
ret = via_pci_setup_mmio(&global_dev);
if (ret)
.probe = via_pci_probe,
.remove = __devexit_p(via_pci_remove),
#ifdef CONFIG_PM
- .suspend = viafb_suspend,
- .resume = viafb_resume,
+ .suspend = via_suspend,
+ .resume = via_resume,
#endif
};
via_write_reg_mask(VIASR, gpio->vg_port_index, 0, 0x02);
}
+#ifdef CONFIG_PM
+
+static int viafb_gpio_suspend(void *private)
+{
+ return 0;
+}
+
+static int viafb_gpio_resume(void *private)
+{
+ int i;
+
+ for (i = 0; i < gpio_config.gpio_chip.ngpio; i += 2)
+ viafb_gpio_enable(gpio_config.active_gpios[i]);
+ return 0;
+}
+
+static struct viafb_pm_hooks viafb_gpio_pm_hooks = {
+ .suspend = viafb_gpio_suspend,
+ .resume = viafb_gpio_resume
+};
+#endif /* CONFIG_PM */
+
/*
* Look up a specific gpio and return the number it was assigned.
*/
printk(KERN_ERR "viafb: failed to add gpios (%d)\n", ret);
gpio_config.gpio_chip.ngpio = 0;
}
+#ifdef CONFIG_PM
+ viafb_pm_register(&viafb_gpio_pm_hooks);
+#endif
return ret;
}
unsigned long flags;
int ret = 0, i;
+#ifdef CONFIG_PM
+ viafb_pm_unregister(&viafb_gpio_pm_hooks);
+#endif
+
/*
* Get unregistered.
*/
#ifdef CONFIG_PM
-int viafb_suspend(struct pci_dev *pdev, pm_message_t state)
+static int viafb_suspend(void *unused)
{
- if (state.event == PM_EVENT_SUSPEND) {
- acquire_console_sem();
- fb_set_suspend(viafbinfo, 1);
-
- viafb_sync(viafbinfo);
-
- pci_save_state(pdev);
- pci_disable_device(pdev);
- pci_set_power_state(pdev, pci_choose_state(pdev, state));
- release_console_sem();
- }
+ acquire_console_sem();
+ fb_set_suspend(viafbinfo, 1);
+ viafb_sync(viafbinfo);
+ release_console_sem();
return 0;
}
-int viafb_resume(struct pci_dev *pdev)
+static int viafb_resume(void *unused)
{
acquire_console_sem();
- pci_set_power_state(pdev, PCI_D0);
- pci_restore_state(pdev);
- if (pci_enable_device(pdev))
- goto fail;
- pci_set_master(pdev);
if (viaparinfo->shared->vdev->engine_mmio)
viafb_reset_engine(viaparinfo);
viafb_set_par(viafbinfo);
viafb_set_par(viafbinfo1);
fb_set_suspend(viafbinfo, 0);
-fail:
release_console_sem();
return 0;
}
+static struct viafb_pm_hooks viafb_fb_pm_hooks = {
+ .suspend = viafb_suspend,
+ .resume = viafb_resume
+};
+
#endif
viafb_init_proc(viaparinfo->shared);
viafb_init_dac(IGA2);
+
+#ifdef CONFIG_PM
+ viafb_pm_register(&viafb_fb_pm_hooks);
+#endif
return 0;
out_fb_unreg:
/* Temporary */
int viafb_init(void);
void viafb_exit(void);
-int viafb_suspend(struct pci_dev *pdev, pm_message_t state);
-int viafb_resume(struct pci_dev *pdev);
#endif /* __VIAFBDEV_H__ */
--- /dev/null
+/*
+ * linux/drivers/video/vt8500lcdfb.c
+ *
+ * Copyright (C) 2010 Alexey Charkov <alchark@gmail.com>
+ *
+ * Based on skeletonfb.c and pxafb.c
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/errno.h>
+#include <linux/string.h>
+#include <linux/mm.h>
+#include <linux/slab.h>
+#include <linux/delay.h>
+#include <linux/fb.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/dma-mapping.h>
+#include <linux/platform_device.h>
+#include <linux/wait.h>
+
+#include <mach/vt8500fb.h>
+
+#include "vt8500lcdfb.h"
+#include "wmt_ge_rops.h"
+
+#define to_vt8500lcd_info(__info) container_of(__info, \
+ struct vt8500lcd_info, fb)
+
+static int vt8500lcd_set_par(struct fb_info *info)
+{
+ struct vt8500lcd_info *fbi = to_vt8500lcd_info(info);
+ int reg_bpp = 5; /* 16bpp */
+ int i;
+ unsigned long control0;
+
+ if (!fbi)
+ return -EINVAL;
+
+ if (info->var.bits_per_pixel <= 8) {
+ /* palettized */
+ info->var.red.offset = 0;
+ info->var.red.length = info->var.bits_per_pixel;
+ info->var.red.msb_right = 0;
+
+ info->var.green.offset = 0;
+ info->var.green.length = info->var.bits_per_pixel;
+ info->var.green.msb_right = 0;
+
+ info->var.blue.offset = 0;
+ info->var.blue.length = info->var.bits_per_pixel;
+ info->var.blue.msb_right = 0;
+
+ info->var.transp.offset = 0;
+ info->var.transp.length = 0;
+ info->var.transp.msb_right = 0;
+
+ info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
+ info->fix.line_length = info->var.xres_virtual /
+ (8/info->var.bits_per_pixel);
+ } else {
+ /* non-palettized */
+ info->var.transp.offset = 0;
+ info->var.transp.length = 0;
+ info->var.transp.msb_right = 0;
+
+ if (info->var.bits_per_pixel == 16) {
+ /* RGB565 */
+ info->var.red.offset = 11;
+ info->var.red.length = 5;
+ info->var.red.msb_right = 0;
+ info->var.green.offset = 5;
+ info->var.green.length = 6;
+ info->var.green.msb_right = 0;
+ info->var.blue.offset = 0;
+ info->var.blue.length = 5;
+ info->var.blue.msb_right = 0;
+ } else {
+ /* Equal depths per channel */
+ info->var.red.offset = info->var.bits_per_pixel
+ * 2 / 3;
+ info->var.red.length = info->var.bits_per_pixel / 3;
+ info->var.red.msb_right = 0;
+ info->var.green.offset = info->var.bits_per_pixel / 3;
+ info->var.green.length = info->var.bits_per_pixel / 3;
+ info->var.green.msb_right = 0;
+ info->var.blue.offset = 0;
+ info->var.blue.length = info->var.bits_per_pixel / 3;
+ info->var.blue.msb_right = 0;
+ }
+
+ info->fix.visual = FB_VISUAL_TRUECOLOR;
+ info->fix.line_length = info->var.bits_per_pixel > 16 ?
+ info->var.xres_virtual << 2 :
+ info->var.xres_virtual << 1;
+ }
+
+ for (i = 0; i < 8; i++) {
+ if (bpp_values[i] == info->var.bits_per_pixel) {
+ reg_bpp = i;
+ continue;
+ }
+ }
+
+ control0 = readl(fbi->regbase) & ~0xf;
+ writel(0, fbi->regbase);
+ while (readl(fbi->regbase + 0x38) & 0x10)
+ /* wait */;
+ writel((((info->var.hsync_len - 1) & 0x3f) << 26)
+ | ((info->var.left_margin & 0xff) << 18)
+ | (((info->var.xres - 1) & 0x3ff) << 8)
+ | (info->var.right_margin & 0xff), fbi->regbase + 0x4);
+ writel((((info->var.vsync_len - 1) & 0x3f) << 26)
+ | ((info->var.upper_margin & 0xff) << 18)
+ | (((info->var.yres - 1) & 0x3ff) << 8)
+ | (info->var.lower_margin & 0xff), fbi->regbase + 0x8);
+ writel((((info->var.yres - 1) & 0x400) << 2)
+ | ((info->var.xres - 1) & 0x400), fbi->regbase + 0x10);
+ writel(0x80000000, fbi->regbase + 0x20);
+ writel(control0 | (reg_bpp << 1) | 0x100, fbi->regbase);
+
+ return 0;
+}
+
+static inline u_int chan_to_field(u_int chan, struct fb_bitfield *bf)
+{
+ chan &= 0xffff;
+ chan >>= 16 - bf->length;
+ return chan << bf->offset;
+}
+
+static int vt8500lcd_setcolreg(unsigned regno, unsigned red, unsigned green,
+ unsigned blue, unsigned transp,
+ struct fb_info *info) {
+ struct vt8500lcd_info *fbi = to_vt8500lcd_info(info);
+ int ret = 1;
+ unsigned int val;
+ if (regno >= 256)
+ return -EINVAL;
+
+ if (info->var.grayscale)
+ red = green = blue =
+ (19595 * red + 38470 * green + 7471 * blue) >> 16;
+
+ switch (fbi->fb.fix.visual) {
+ case FB_VISUAL_TRUECOLOR:
+ if (regno < 16) {
+ u32 *pal = fbi->fb.pseudo_palette;
+
+ val = chan_to_field(red, &fbi->fb.var.red);
+ val |= chan_to_field(green, &fbi->fb.var.green);
+ val |= chan_to_field(blue, &fbi->fb.var.blue);
+
+ pal[regno] = val;
+ ret = 0;
+ }
+ break;
+
+ case FB_VISUAL_STATIC_PSEUDOCOLOR:
+ case FB_VISUAL_PSEUDOCOLOR:
+ writew((red & 0xf800)
+ | ((green >> 5) & 0x7e0)
+ | ((blue >> 11) & 0x1f),
+ fbi->palette_cpu + sizeof(u16) * regno);
+ break;
+ }
+
+ return ret;
+}
+
+static int vt8500lcd_ioctl(struct fb_info *info, unsigned int cmd,
+ unsigned long arg)
+{
+ int ret = 0;
+ struct vt8500lcd_info *fbi = to_vt8500lcd_info(info);
+
+ if (cmd == FBIO_WAITFORVSYNC) {
+ /* Unmask End of Frame interrupt */
+ writel(0xffffffff ^ (1 << 3), fbi->regbase + 0x3c);
+ ret = wait_event_interruptible_timeout(fbi->wait,
+ readl(fbi->regbase + 0x38) & (1 << 3), HZ / 10);
+ /* Mask back to reduce unwanted interrupt traffic */
+ writel(0xffffffff, fbi->regbase + 0x3c);
+ if (ret < 0)
+ return ret;
+ if (ret == 0)
+ return -ETIMEDOUT;
+ }
+
+ return ret;
+}
+
+static int vt8500lcd_pan_display(struct fb_var_screeninfo *var,
+ struct fb_info *info)
+{
+ unsigned pixlen = info->fix.line_length / info->var.xres_virtual;
+ unsigned off = pixlen * var->xoffset
+ + info->fix.line_length * var->yoffset;
+ struct vt8500lcd_info *fbi = to_vt8500lcd_info(info);
+
+ writel((1 << 31)
+ | (((var->xres_virtual - var->xres) * pixlen / 4) << 20)
+ | (off >> 2), fbi->regbase + 0x20);
+ return 0;
+}
+
+static struct fb_ops vt8500lcd_ops = {
+ .owner = THIS_MODULE,
+ .fb_set_par = vt8500lcd_set_par,
+ .fb_setcolreg = vt8500lcd_setcolreg,
+ .fb_fillrect = wmt_ge_fillrect,
+ .fb_copyarea = wmt_ge_copyarea,
+ .fb_imageblit = sys_imageblit,
+ .fb_sync = wmt_ge_sync,
+ .fb_ioctl = vt8500lcd_ioctl,
+ .fb_pan_display = vt8500lcd_pan_display,
+};
+
+static irqreturn_t vt8500lcd_handle_irq(int irq, void *dev_id)
+{
+ struct vt8500lcd_info *fbi = dev_id;
+
+ if (readl(fbi->regbase + 0x38) & (1 << 3))
+ wake_up_interruptible(&fbi->wait);
+
+ writel(0xffffffff, fbi->regbase + 0x38);
+ return IRQ_HANDLED;
+}
+
+static int __devinit vt8500lcd_probe(struct platform_device *pdev)
+{
+ struct vt8500lcd_info *fbi;
+ struct resource *res;
+ struct vt8500fb_platform_data *pdata = pdev->dev.platform_data;
+ void *addr;
+ int irq, ret;
+
+ ret = -ENOMEM;
+ fbi = NULL;
+
+ fbi = kzalloc(sizeof(struct vt8500lcd_info) + sizeof(u32) * 16,
+ GFP_KERNEL);
+ if (!fbi) {
+ dev_err(&pdev->dev, "Failed to initialize framebuffer device\n");
+ ret = -ENOMEM;
+ goto failed;
+ }
+
+ strcpy(fbi->fb.fix.id, "VT8500 LCD");
+
+ fbi->fb.fix.type = FB_TYPE_PACKED_PIXELS;
+ fbi->fb.fix.xpanstep = 0;
+ fbi->fb.fix.ypanstep = 1;
+ fbi->fb.fix.ywrapstep = 0;
+ fbi->fb.fix.accel = FB_ACCEL_NONE;
+
+ fbi->fb.var.nonstd = 0;
+ fbi->fb.var.activate = FB_ACTIVATE_NOW;
+ fbi->fb.var.height = -1;
+ fbi->fb.var.width = -1;
+ fbi->fb.var.vmode = FB_VMODE_NONINTERLACED;
+
+ fbi->fb.fbops = &vt8500lcd_ops;
+ fbi->fb.flags = FBINFO_DEFAULT
+ | FBINFO_HWACCEL_COPYAREA
+ | FBINFO_HWACCEL_FILLRECT
+ | FBINFO_HWACCEL_YPAN
+ | FBINFO_VIRTFB
+ | FBINFO_PARTIAL_PAN_OK;
+ fbi->fb.node = -1;
+
+ addr = fbi;
+ addr = addr + sizeof(struct vt8500lcd_info);
+ fbi->fb.pseudo_palette = addr;
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ if (res == NULL) {
+ dev_err(&pdev->dev, "no I/O memory resource defined\n");
+ ret = -ENODEV;
+ goto failed_fbi;
+ }
+
+ res = request_mem_region(res->start, resource_size(res), "vt8500lcd");
+ if (res == NULL) {
+ dev_err(&pdev->dev, "failed to request I/O memory\n");
+ ret = -EBUSY;
+ goto failed_fbi;
+ }
+
+ fbi->regbase = ioremap(res->start, resource_size(res));
+ if (fbi->regbase == NULL) {
+ dev_err(&pdev->dev, "failed to map I/O memory\n");
+ ret = -EBUSY;
+ goto failed_free_res;
+ }
+
+ fbi->fb.fix.smem_start = pdata->video_mem_phys;
+ fbi->fb.fix.smem_len = pdata->video_mem_len;
+ fbi->fb.screen_base = pdata->video_mem_virt;
+
+ fbi->palette_size = PAGE_ALIGN(512);
+ fbi->palette_cpu = dma_alloc_coherent(&pdev->dev,
+ fbi->palette_size,
+ &fbi->palette_phys,
+ GFP_KERNEL);
+ if (fbi->palette_cpu == NULL) {
+ dev_err(&pdev->dev, "Failed to allocate palette buffer\n");
+ ret = -ENOMEM;
+ goto failed_free_io;
+ }
+
+ irq = platform_get_irq(pdev, 0);
+ if (irq < 0) {
+ dev_err(&pdev->dev, "no IRQ defined\n");
+ ret = -ENODEV;
+ goto failed_free_palette;
+ }
+
+ ret = request_irq(irq, vt8500lcd_handle_irq, IRQF_DISABLED, "LCD", fbi);
+ if (ret) {
+ dev_err(&pdev->dev, "request_irq failed: %d\n", ret);
+ ret = -EBUSY;
+ goto failed_free_palette;
+ }
+
+ init_waitqueue_head(&fbi->wait);
+
+ if (fb_alloc_cmap(&fbi->fb.cmap, 256, 0) < 0) {
+ dev_err(&pdev->dev, "Failed to allocate color map\n");
+ ret = -ENOMEM;
+ goto failed_free_irq;
+ }
+
+ fb_videomode_to_var(&fbi->fb.var, &pdata->mode);
+ fbi->fb.var.bits_per_pixel = pdata->bpp;
+ fbi->fb.var.xres_virtual = pdata->xres_virtual;
+ fbi->fb.var.yres_virtual = pdata->yres_virtual;
+
+ ret = vt8500lcd_set_par(&fbi->fb);
+ if (ret) {
+ dev_err(&pdev->dev, "Failed to set parameters\n");
+ goto failed_free_cmap;
+ }
+
+ writel(fbi->fb.fix.smem_start >> 22, fbi->regbase + 0x1c);
+ writel((fbi->palette_phys & 0xfffffe00) | 1, fbi->regbase + 0x18);
+
+ platform_set_drvdata(pdev, fbi);
+
+ ret = register_framebuffer(&fbi->fb);
+ if (ret < 0) {
+ dev_err(&pdev->dev,
+ "Failed to register framebuffer device: %d\n", ret);
+ goto failed_free_cmap;
+ }
+
+ /*
+ * Ok, now enable the LCD controller
+ */
+ writel(readl(fbi->regbase) | 1, fbi->regbase);
+
+ return 0;
+
+failed_free_cmap:
+ if (fbi->fb.cmap.len)
+ fb_dealloc_cmap(&fbi->fb.cmap);
+failed_free_irq:
+ free_irq(irq, fbi);
+failed_free_palette:
+ dma_free_coherent(&pdev->dev, fbi->palette_size,
+ fbi->palette_cpu, fbi->palette_phys);
+failed_free_io:
+ iounmap(fbi->regbase);
+failed_free_res:
+ release_mem_region(res->start, resource_size(res));
+failed_fbi:
+ platform_set_drvdata(pdev, NULL);
+ kfree(fbi);
+failed:
+ return ret;
+}
+
+static int __devexit vt8500lcd_remove(struct platform_device *pdev)
+{
+ struct vt8500lcd_info *fbi = platform_get_drvdata(pdev);
+ struct resource *res;
+ int irq;
+
+ unregister_framebuffer(&fbi->fb);
+
+ writel(0, fbi->regbase);
+
+ if (fbi->fb.cmap.len)
+ fb_dealloc_cmap(&fbi->fb.cmap);
+
+ irq = platform_get_irq(pdev, 0);
+ free_irq(irq, fbi);
+
+ dma_free_coherent(&pdev->dev, fbi->palette_size,
+ fbi->palette_cpu, fbi->palette_phys);
+
+ iounmap(fbi->regbase);
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ release_mem_region(res->start, resource_size(res));
+
+ kfree(fbi);
+
+ return 0;
+}
+
+static struct platform_driver vt8500lcd_driver = {
+ .probe = vt8500lcd_probe,
+ .remove = __devexit_p(vt8500lcd_remove),
+ .driver = {
+ .owner = THIS_MODULE,
+ .name = "vt8500-lcd",
+ },
+};
+
+static int __init vt8500lcd_init(void)
+{
+ return platform_driver_register(&vt8500lcd_driver);
+}
+
+static void __exit vt8500lcd_exit(void)
+{
+ platform_driver_unregister(&vt8500lcd_driver);
+}
+
+module_init(vt8500lcd_init);
+module_exit(vt8500lcd_exit);
+
+MODULE_AUTHOR("Alexey Charkov <alchark@gmail.com>");
+MODULE_DESCRIPTION("LCD controller driver for VIA VT8500");
+MODULE_LICENSE("GPL");
--- /dev/null
+/*
+ * linux/drivers/video/vt8500lcdfb.h
+ *
+ * Copyright (C) 2010 Alexey Charkov <alchark@gmail.com>
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+struct vt8500lcd_info {
+ struct fb_info fb;
+ void __iomem *regbase;
+ void __iomem *palette_cpu;
+ dma_addr_t palette_phys;
+ size_t palette_size;
+ wait_queue_head_t wait;
+};
+
+static int bpp_values[] = {
+ 1,
+ 2,
+ 4,
+ 8,
+ 12,
+ 16,
+ 18,
+ 24,
+};
--- /dev/null
+/*
+ * WonderMedia WM8505 Frame Buffer device driver
+ *
+ * Copyright (C) 2010 Ed Spiridonov <edo.rus@gmail.com>
+ * Based on vt8500lcdfb.c
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/errno.h>
+#include <linux/string.h>
+#include <linux/mm.h>
+#include <linux/slab.h>
+#include <linux/delay.h>
+#include <linux/fb.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/dma-mapping.h>
+#include <linux/platform_device.h>
+#include <linux/wait.h>
+
+#include <mach/vt8500fb.h>
+
+#include "wm8505fb_regs.h"
+#include "wmt_ge_rops.h"
+
+#define DRIVER_NAME "wm8505-fb"
+
+#define to_wm8505fb_info(__info) container_of(__info, \
+ struct wm8505fb_info, fb)
+struct wm8505fb_info {
+ struct fb_info fb;
+ void __iomem *regbase;
+ unsigned int contrast;
+};
+
+
+static int wm8505fb_init_hw(struct fb_info *info)
+{
+ struct wm8505fb_info *fbi = to_wm8505fb_info(info);
+
+ int i;
+
+ /* I know the purpose only of few registers, so clear unknown */
+ for (i = 0; i < 0x200; i += 4)
+ writel(0, fbi->regbase + i);
+
+ /* Set frame buffer address */
+ writel(fbi->fb.fix.smem_start, fbi->regbase + WMT_GOVR_FBADDR);
+ writel(fbi->fb.fix.smem_start, fbi->regbase + WMT_GOVR_FBADDR1);
+
+ /* Set in-memory picture format to RGB 32bpp */
+ writel(0x1c, fbi->regbase + WMT_GOVR_COLORSPACE);
+ writel(1, fbi->regbase + WMT_GOVR_COLORSPACE1);
+
+ /* Virtual buffer size */
+ writel(info->var.xres, fbi->regbase + WMT_GOVR_XRES);
+ writel(info->var.xres_virtual, fbi->regbase + WMT_GOVR_XRES_VIRTUAL);
+
+ /* black magic ;) */
+ writel(0xf, fbi->regbase + WMT_GOVR_FHI);
+ writel(4, fbi->regbase + WMT_GOVR_DVO_SET);
+ writel(1, fbi->regbase + WMT_GOVR_MIF_ENABLE);
+ writel(1, fbi->regbase + WMT_GOVR_REG_UPDATE);
+
+ return 0;
+}
+
+static int wm8505fb_set_timing(struct fb_info *info)
+{
+ struct wm8505fb_info *fbi = to_wm8505fb_info(info);
+
+ int h_start = info->var.left_margin;
+ int h_end = h_start + info->var.xres;
+ int h_all = h_end + info->var.right_margin;
+ int h_sync = info->var.hsync_len;
+
+ int v_start = info->var.upper_margin;
+ int v_end = v_start + info->var.yres;
+ int v_all = v_end + info->var.lower_margin;
+ int v_sync = info->var.vsync_len;
+
+ writel(0, fbi->regbase + WMT_GOVR_TG);
+
+ writel(h_start, fbi->regbase + WMT_GOVR_TIMING_H_START);
+ writel(h_end, fbi->regbase + WMT_GOVR_TIMING_H_END);
+ writel(h_all, fbi->regbase + WMT_GOVR_TIMING_H_ALL);
+ writel(h_sync, fbi->regbase + WMT_GOVR_TIMING_H_SYNC);
+
+ writel(v_start, fbi->regbase + WMT_GOVR_TIMING_V_START);
+ writel(v_end, fbi->regbase + WMT_GOVR_TIMING_V_END);
+ writel(v_all, fbi->regbase + WMT_GOVR_TIMING_V_ALL);
+ writel(v_sync, fbi->regbase + WMT_GOVR_TIMING_V_SYNC);
+
+ writel(1, fbi->regbase + WMT_GOVR_TG);
+
+ return 0;
+}
+
+
+static int wm8505fb_set_par(struct fb_info *info)
+{
+ struct wm8505fb_info *fbi = to_wm8505fb_info(info);
+
+ if (!fbi)
+ return -EINVAL;
+
+ if (info->var.bits_per_pixel == 32) {
+ info->var.red.offset = 16;
+ info->var.red.length = 8;
+ info->var.red.msb_right = 0;
+ info->var.green.offset = 8;
+ info->var.green.length = 8;
+ info->var.green.msb_right = 0;
+ info->var.blue.offset = 0;
+ info->var.blue.length = 8;
+ info->var.blue.msb_right = 0;
+ info->fix.visual = FB_VISUAL_TRUECOLOR;
+ info->fix.line_length = info->var.xres_virtual << 2;
+ }
+
+ wm8505fb_set_timing(info);
+
+ writel(fbi->contrast<<16 | fbi->contrast<<8 | fbi->contrast,
+ fbi->regbase + WMT_GOVR_CONTRAST);
+
+ return 0;
+}
+
+static ssize_t contrast_show(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ struct fb_info *info = dev_get_drvdata(dev);
+ struct wm8505fb_info *fbi = to_wm8505fb_info(info);
+
+ return sprintf(buf, "%d\n", fbi->contrast);
+}
+
+static ssize_t contrast_store(struct device *dev,
+ struct device_attribute *attr,
+ const char *buf, size_t count)
+{
+ struct fb_info *info = dev_get_drvdata(dev);
+ struct wm8505fb_info *fbi = to_wm8505fb_info(info);
+ unsigned long tmp;
+
+ if (strict_strtoul(buf, 10, &tmp) || (tmp > 0xff))
+ return -EINVAL;
+ fbi->contrast = tmp;
+
+ wm8505fb_set_par(info);
+
+ return count;
+}
+
+static DEVICE_ATTR(contrast, 0644, contrast_show, contrast_store);
+
+static inline u_int chan_to_field(u_int chan, struct fb_bitfield *bf)
+{
+ chan &= 0xffff;
+ chan >>= 16 - bf->length;
+ return chan << bf->offset;
+}
+
+static int wm8505fb_setcolreg(unsigned regno, unsigned red, unsigned green,
+ unsigned blue, unsigned transp,
+ struct fb_info *info) {
+ struct wm8505fb_info *fbi = to_wm8505fb_info(info);
+ int ret = 1;
+ unsigned int val;
+ if (regno >= 256)
+ return -EINVAL;
+
+ if (info->var.grayscale)
+ red = green = blue =
+ (19595 * red + 38470 * green + 7471 * blue) >> 16;
+
+ switch (fbi->fb.fix.visual) {
+ case FB_VISUAL_TRUECOLOR:
+ if (regno < 16) {
+ u32 *pal = info->pseudo_palette;
+
+ val = chan_to_field(red, &fbi->fb.var.red);
+ val |= chan_to_field(green, &fbi->fb.var.green);
+ val |= chan_to_field(blue, &fbi->fb.var.blue);
+
+ pal[regno] = val;
+ ret = 0;
+ }
+ break;
+ }
+
+ return ret;
+}
+
+static int wm8505fb_pan_display(struct fb_var_screeninfo *var,
+ struct fb_info *info)
+{
+ struct wm8505fb_info *fbi = to_wm8505fb_info(info);
+
+ writel(var->xoffset, fbi->regbase + WMT_GOVR_XPAN);
+ writel(var->yoffset, fbi->regbase + WMT_GOVR_YPAN);
+ return 0;
+}
+
+static int wm8505fb_blank(int blank, struct fb_info *info)
+{
+ struct wm8505fb_info *fbi = to_wm8505fb_info(info);
+
+ switch (blank) {
+ case FB_BLANK_UNBLANK:
+ wm8505fb_set_timing(info);
+ break;
+ default:
+ writel(0, fbi->regbase + WMT_GOVR_TIMING_V_SYNC);
+ break;
+ }
+
+ return 0;
+}
+
+static struct fb_ops wm8505fb_ops = {
+ .owner = THIS_MODULE,
+ .fb_set_par = wm8505fb_set_par,
+ .fb_setcolreg = wm8505fb_setcolreg,
+ .fb_fillrect = wmt_ge_fillrect,
+ .fb_copyarea = wmt_ge_copyarea,
+ .fb_imageblit = sys_imageblit,
+ .fb_sync = wmt_ge_sync,
+ .fb_pan_display = wm8505fb_pan_display,
+ .fb_blank = wm8505fb_blank,
+};
+
+static int __devinit wm8505fb_probe(struct platform_device *pdev)
+{
+ struct wm8505fb_info *fbi;
+ struct resource *res;
+ void *addr;
+ struct vt8500fb_platform_data *pdata;
+ int ret;
+
+ pdata = pdev->dev.platform_data;
+
+ ret = -ENOMEM;
+ fbi = NULL;
+
+ fbi = kzalloc(sizeof(struct wm8505fb_info) + sizeof(u32) * 16,
+ GFP_KERNEL);
+ if (!fbi) {
+ dev_err(&pdev->dev, "Failed to initialize framebuffer device\n");
+ ret = -ENOMEM;
+ goto failed;
+ }
+
+ strcpy(fbi->fb.fix.id, DRIVER_NAME);
+
+ fbi->fb.fix.type = FB_TYPE_PACKED_PIXELS;
+ fbi->fb.fix.xpanstep = 1;
+ fbi->fb.fix.ypanstep = 1;
+ fbi->fb.fix.ywrapstep = 0;
+ fbi->fb.fix.accel = FB_ACCEL_NONE;
+
+ fbi->fb.fbops = &wm8505fb_ops;
+ fbi->fb.flags = FBINFO_DEFAULT
+ | FBINFO_HWACCEL_COPYAREA
+ | FBINFO_HWACCEL_FILLRECT
+ | FBINFO_HWACCEL_XPAN
+ | FBINFO_HWACCEL_YPAN
+ | FBINFO_VIRTFB
+ | FBINFO_PARTIAL_PAN_OK;
+ fbi->fb.node = -1;
+
+ addr = fbi;
+ addr = addr + sizeof(struct wm8505fb_info);
+ fbi->fb.pseudo_palette = addr;
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ if (res == NULL) {
+ dev_err(&pdev->dev, "no I/O memory resource defined\n");
+ ret = -ENODEV;
+ goto failed_fbi;
+ }
+
+ res = request_mem_region(res->start, resource_size(res), DRIVER_NAME);
+ if (res == NULL) {
+ dev_err(&pdev->dev, "failed to request I/O memory\n");
+ ret = -EBUSY;
+ goto failed_fbi;
+ }
+
+ fbi->regbase = ioremap(res->start, resource_size(res));
+ if (fbi->regbase == NULL) {
+ dev_err(&pdev->dev, "failed to map I/O memory\n");
+ ret = -EBUSY;
+ goto failed_free_res;
+ }
+
+ fb_videomode_to_var(&fbi->fb.var, &pdata->mode);
+
+ fbi->fb.var.nonstd = 0;
+ fbi->fb.var.activate = FB_ACTIVATE_NOW;
+
+ fbi->fb.var.height = -1;
+ fbi->fb.var.width = -1;
+ fbi->fb.var.xres_virtual = pdata->xres_virtual;
+ fbi->fb.var.yres_virtual = pdata->yres_virtual;
+ fbi->fb.var.bits_per_pixel = pdata->bpp;
+
+ fbi->fb.fix.smem_start = pdata->video_mem_phys;
+ fbi->fb.fix.smem_len = pdata->video_mem_len;
+ fbi->fb.screen_base = pdata->video_mem_virt;
+ fbi->fb.screen_size = pdata->video_mem_len;
+
+ if (fb_alloc_cmap(&fbi->fb.cmap, 256, 0) < 0) {
+ dev_err(&pdev->dev, "Failed to allocate color map\n");
+ ret = -ENOMEM;
+ goto failed_free_io;
+ }
+
+ wm8505fb_init_hw(&fbi->fb);
+
+ fbi->contrast = 0x80;
+ ret = wm8505fb_set_par(&fbi->fb);
+ if (ret) {
+ dev_err(&pdev->dev, "Failed to set parameters\n");
+ goto failed_free_cmap;
+ }
+
+ platform_set_drvdata(pdev, fbi);
+
+ ret = register_framebuffer(&fbi->fb);
+ if (ret < 0) {
+ dev_err(&pdev->dev,
+ "Failed to register framebuffer device: %d\n", ret);
+ goto failed_free_cmap;
+ }
+
+ ret = device_create_file(&pdev->dev, &dev_attr_contrast);
+ if (ret < 0) {
+ printk(KERN_WARNING "fb%d: failed to register attributes (%d)\n",
+ fbi->fb.node, ret);
+ }
+
+ printk(KERN_INFO "fb%d: %s frame buffer at 0x%lx-0x%lx\n",
+ fbi->fb.node, fbi->fb.fix.id, fbi->fb.fix.smem_start,
+ fbi->fb.fix.smem_start + fbi->fb.fix.smem_len - 1);
+
+ return 0;
+
+failed_free_cmap:
+ if (fbi->fb.cmap.len)
+ fb_dealloc_cmap(&fbi->fb.cmap);
+failed_free_io:
+ iounmap(fbi->regbase);
+failed_free_res:
+ release_mem_region(res->start, resource_size(res));
+failed_fbi:
+ platform_set_drvdata(pdev, NULL);
+ kfree(fbi);
+failed:
+ return ret;
+}
+
+static int __devexit wm8505fb_remove(struct platform_device *pdev)
+{
+ struct wm8505fb_info *fbi = platform_get_drvdata(pdev);
+ struct resource *res;
+
+ device_remove_file(&pdev->dev, &dev_attr_contrast);
+
+ unregister_framebuffer(&fbi->fb);
+
+ writel(0, fbi->regbase);
+
+ if (fbi->fb.cmap.len)
+ fb_dealloc_cmap(&fbi->fb.cmap);
+
+ iounmap(fbi->regbase);
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ release_mem_region(res->start, resource_size(res));
+
+ kfree(fbi);
+
+ return 0;
+}
+
+static struct platform_driver wm8505fb_driver = {
+ .probe = wm8505fb_probe,
+ .remove = __devexit_p(wm8505fb_remove),
+ .driver = {
+ .owner = THIS_MODULE,
+ .name = DRIVER_NAME,
+ },
+};
+
+static int __init wm8505fb_init(void)
+{
+ return platform_driver_register(&wm8505fb_driver);
+}
+
+static void __exit wm8505fb_exit(void)
+{
+ platform_driver_unregister(&wm8505fb_driver);
+}
+
+module_init(wm8505fb_init);
+module_exit(wm8505fb_exit);
+
+MODULE_AUTHOR("Ed Spiridonov <edo.rus@gmail.com>");
+MODULE_DESCRIPTION("Framebuffer driver for WMT WM8505");
+MODULE_LICENSE("GPL");
--- /dev/null
+/*
+ * GOVR registers list for WM8505 chips
+ *
+ * Copyright (C) 2010 Ed Spiridonov <edo.rus@gmail.com>
+ * Based on VIA/WonderMedia wm8510-govrh-reg.h
+ * http://github.com/projectgus/kernel_wm8505/blob/wm8505_2.6.29/
+ * drivers/video/wmt/register/wm8510/wm8510-govrh-reg.h
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _WM8505FB_REGS_H
+#define _WM8505FB_REGS_H
+
+/*
+ * Color space select register, default value 0x1c
+ * BIT0 GOVRH_DVO_YUV2RGB_ENABLE
+ * BIT1 GOVRH_VGA_YUV2RGB_ENABLE
+ * BIT2 GOVRH_RGB_MODE
+ * BIT3 GOVRH_DAC_CLKINV
+ * BIT4 GOVRH_BLANK_ZERO
+ */
+#define WMT_GOVR_COLORSPACE 0x1e4
+/*
+ * Another colorspace select register, default value 1
+ * BIT0 GOVRH_DVO_RGB
+ * BIT1 GOVRH_DVO_YUV422
+ */
+#define WMT_GOVR_COLORSPACE1 0x30
+
+#define WMT_GOVR_CONTRAST 0x1b8
+#define WMT_GOVR_BRGHTNESS 0x1bc /* incompatible with RGB? */
+
+/* Framubeffer address */
+#define WMT_GOVR_FBADDR 0x90
+#define WMT_GOVR_FBADDR1 0x94 /* UV offset in YUV mode */
+
+/* Offset of visible window */
+#define WMT_GOVR_XPAN 0xa4
+#define WMT_GOVR_YPAN 0xa0
+
+#define WMT_GOVR_XRES 0x98
+#define WMT_GOVR_XRES_VIRTUAL 0x9c
+
+#define WMT_GOVR_MIF_ENABLE 0x80
+#define WMT_GOVR_FHI 0xa8
+#define WMT_GOVR_REG_UPDATE 0xe4
+
+/*
+ * BIT0 GOVRH_DVO_OUTWIDTH
+ * BIT1 GOVRH_DVO_SYNC_POLAR
+ * BIT2 GOVRH_DVO_ENABLE
+ */
+#define WMT_GOVR_DVO_SET 0x148
+
+/* Timing generator? */
+#define WMT_GOVR_TG 0x100
+
+/* Timings */
+#define WMT_GOVR_TIMING_H_ALL 0x108
+#define WMT_GOVR_TIMING_V_ALL 0x10c
+#define WMT_GOVR_TIMING_V_START 0x110
+#define WMT_GOVR_TIMING_V_END 0x114
+#define WMT_GOVR_TIMING_H_START 0x118
+#define WMT_GOVR_TIMING_H_END 0x11c
+#define WMT_GOVR_TIMING_V_SYNC 0x128
+#define WMT_GOVR_TIMING_H_SYNC 0x12c
+
+#endif /* _WM8505FB_REGS_H */
--- /dev/null
+/*
+ * linux/drivers/video/wmt_ge_rops.c
+ *
+ * Accelerators for raster operations using WonderMedia Graphics Engine
+ *
+ * Copyright (C) 2010 Alexey Charkov <alchark@gmail.com>
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/module.h>
+#include <linux/fb.h>
+#include <linux/platform_device.h>
+#include "fb_draw.h"
+
+#define GE_COMMAND_OFF 0x00
+#define GE_DEPTH_OFF 0x04
+#define GE_HIGHCOLOR_OFF 0x08
+#define GE_ROPCODE_OFF 0x14
+#define GE_FIRE_OFF 0x18
+#define GE_SRCBASE_OFF 0x20
+#define GE_SRCDISPW_OFF 0x24
+#define GE_SRCDISPH_OFF 0x28
+#define GE_SRCAREAX_OFF 0x2c
+#define GE_SRCAREAY_OFF 0x30
+#define GE_SRCAREAW_OFF 0x34
+#define GE_SRCAREAH_OFF 0x38
+#define GE_DESTBASE_OFF 0x3c
+#define GE_DESTDISPW_OFF 0x40
+#define GE_DESTDISPH_OFF 0x44
+#define GE_DESTAREAX_OFF 0x48
+#define GE_DESTAREAY_OFF 0x4c
+#define GE_DESTAREAW_OFF 0x50
+#define GE_DESTAREAH_OFF 0x54
+#define GE_PAT0C_OFF 0x88 /* Pattern 0 color */
+#define GE_ENABLE_OFF 0xec
+#define GE_INTEN_OFF 0xf0
+#define GE_STATUS_OFF 0xf8
+
+static void __iomem *regbase;
+
+void wmt_ge_fillrect(struct fb_info *p, const struct fb_fillrect *rect)
+{
+ unsigned long fg, pat;
+
+ if (p->state != FBINFO_STATE_RUNNING)
+ return;
+
+ if (p->fix.visual == FB_VISUAL_TRUECOLOR ||
+ p->fix.visual == FB_VISUAL_DIRECTCOLOR)
+ fg = ((u32 *) (p->pseudo_palette))[rect->color];
+ else
+ fg = rect->color;
+
+ pat = pixel_to_pat(p->var.bits_per_pixel, fg);
+
+ if (p->fbops->fb_sync)
+ p->fbops->fb_sync(p);
+
+ writel(p->var.bits_per_pixel == 32 ? 3 :
+ (p->var.bits_per_pixel == 8 ? 0 : 1), regbase + GE_DEPTH_OFF);
+ writel(p->var.bits_per_pixel == 15 ? 1 : 0, regbase + GE_HIGHCOLOR_OFF);
+ writel(p->fix.smem_start, regbase + GE_DESTBASE_OFF);
+ writel(p->var.xres_virtual - 1, regbase + GE_DESTDISPW_OFF);
+ writel(p->var.yres_virtual - 1, regbase + GE_DESTDISPH_OFF);
+ writel(rect->dx, regbase + GE_DESTAREAX_OFF);
+ writel(rect->dy, regbase + GE_DESTAREAY_OFF);
+ writel(rect->width - 1, regbase + GE_DESTAREAW_OFF);
+ writel(rect->height - 1, regbase + GE_DESTAREAH_OFF);
+
+ writel(pat, regbase + GE_PAT0C_OFF);
+ writel(1, regbase + GE_COMMAND_OFF);
+ writel(rect->rop == ROP_XOR ? 0x5a : 0xf0, regbase + GE_ROPCODE_OFF);
+ writel(1, regbase + GE_FIRE_OFF);
+}
+EXPORT_SYMBOL_GPL(wmt_ge_fillrect);
+
+void wmt_ge_copyarea(struct fb_info *p, const struct fb_copyarea *area)
+{
+ if (p->state != FBINFO_STATE_RUNNING)
+ return;
+
+ if (p->fbops->fb_sync)
+ p->fbops->fb_sync(p);
+
+ writel(p->var.bits_per_pixel > 16 ? 3 :
+ (p->var.bits_per_pixel > 8 ? 1 : 0), regbase + GE_DEPTH_OFF);
+
+ writel(p->fix.smem_start, regbase + GE_SRCBASE_OFF);
+ writel(p->var.xres_virtual - 1, regbase + GE_SRCDISPW_OFF);
+ writel(p->var.yres_virtual - 1, regbase + GE_SRCDISPH_OFF);
+ writel(area->sx, regbase + GE_SRCAREAX_OFF);
+ writel(area->sy, regbase + GE_SRCAREAY_OFF);
+ writel(area->width - 1, regbase + GE_SRCAREAW_OFF);
+ writel(area->height - 1, regbase + GE_SRCAREAH_OFF);
+
+ writel(p->fix.smem_start, regbase + GE_DESTBASE_OFF);
+ writel(p->var.xres_virtual - 1, regbase + GE_DESTDISPW_OFF);
+ writel(p->var.yres_virtual - 1, regbase + GE_DESTDISPH_OFF);
+ writel(area->dx, regbase + GE_DESTAREAX_OFF);
+ writel(area->dy, regbase + GE_DESTAREAY_OFF);
+ writel(area->width - 1, regbase + GE_DESTAREAW_OFF);
+ writel(area->height - 1, regbase + GE_DESTAREAH_OFF);
+
+ writel(0xcc, regbase + GE_ROPCODE_OFF);
+ writel(1, regbase + GE_COMMAND_OFF);
+ writel(1, regbase + GE_FIRE_OFF);
+}
+EXPORT_SYMBOL_GPL(wmt_ge_copyarea);
+
+int wmt_ge_sync(struct fb_info *p)
+{
+ int loops = 5000000;
+ while ((readl(regbase + GE_STATUS_OFF) & 4) && --loops)
+ cpu_relax();
+ return loops > 0 ? 0 : -EBUSY;
+}
+EXPORT_SYMBOL_GPL(wmt_ge_sync);
+
+static int __devinit wmt_ge_rops_probe(struct platform_device *pdev)
+{
+ struct resource *res;
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ if (res == NULL) {
+ dev_err(&pdev->dev, "no I/O memory resource defined\n");
+ return -ENODEV;
+ }
+
+ /* Only one ROP engine is presently supported. */
+ if (unlikely(regbase)) {
+ WARN_ON(1);
+ return -EBUSY;
+ }
+
+ regbase = ioremap(res->start, resource_size(res));
+ if (regbase == NULL) {
+ dev_err(&pdev->dev, "failed to map I/O memory\n");
+ return -EBUSY;
+ }
+
+ writel(1, regbase + GE_ENABLE_OFF);
+ printk(KERN_INFO "Enabled support for WMT GE raster acceleration\n");
+
+ return 0;
+}
+
+static int __devexit wmt_ge_rops_remove(struct platform_device *pdev)
+{
+ iounmap(regbase);
+ return 0;
+}
+
+static struct platform_driver wmt_ge_rops_driver = {
+ .probe = wmt_ge_rops_probe,
+ .remove = __devexit_p(wmt_ge_rops_remove),
+ .driver = {
+ .owner = THIS_MODULE,
+ .name = "wmt_ge_rops",
+ },
+};
+
+static int __init wmt_ge_rops_init(void)
+{
+ return platform_driver_register(&wmt_ge_rops_driver);
+}
+
+static void __exit wmt_ge_rops_exit(void)
+{
+ platform_driver_unregister(&wmt_ge_rops_driver);
+}
+
+module_init(wmt_ge_rops_init);
+module_exit(wmt_ge_rops_exit);
+
+MODULE_AUTHOR("Alexey Charkov <alchark@gmail.com");
+MODULE_DESCRIPTION("Accelerators for raster operations using "
+ "WonderMedia Graphics Engine");
+MODULE_LICENSE("GPL");
--- /dev/null
+extern void wmt_ge_fillrect(struct fb_info *info,
+ const struct fb_fillrect *rect);
+extern void wmt_ge_copyarea(struct fb_info *info,
+ const struct fb_copyarea *area);
+extern int wmt_ge_sync(struct fb_info *info);
extern const unsigned char *fb_firmware_edid(struct device *device);
extern void fb_edid_to_monspecs(unsigned char *edid,
struct fb_monspecs *specs);
+extern void fb_edid_add_monspecs(unsigned char *edid,
+ struct fb_monspecs *specs);
extern void fb_destroy_modedb(struct fb_videomode *modedb);
extern int fb_find_mode_cvt(struct fb_videomode *mode, int margins, int rb);
extern unsigned char *fb_ddc_read(struct i2c_adapter *adapter);
extern const char *fb_mode_option;
extern const struct fb_videomode vesa_modes[];
+extern const struct fb_videomode cea_modes[64];
struct fb_modelist {
struct list_head list;
u8 ioport_index;
};
+/*
+ * Allow subdevs to register suspend/resume hooks.
+ */
+#ifdef CONFIG_PM
+struct viafb_pm_hooks {
+ struct list_head list;
+ int (*suspend)(void *private);
+ int (*resume)(void *private);
+ void *private;
+};
+
+void viafb_pm_register(struct viafb_pm_hooks *hooks);
+void viafb_pm_unregister(struct viafb_pm_hooks *hooks);
+#endif /* CONFIG_PM */
+
/*
* This is the global viafb "device" containing stuff needed by
* all subdevs.
#define S1DREG_DELAYOFF 0xFFFE
#define S1DREG_DELAYON 0xFFFF
-#define BBLT_FIFO_EMPTY 0x00
-#define BBLT_FIFO_NOT_EMPTY 0x40
-#define BBLT_FIFO_NOT_FULL 0x30
-#define BBLT_FIFO_HALF_FULL 0x20
-#define BBLT_FIFO_FULL 0x10
-
#define BBLT_SOLID_FILL 0x0c
struct sh_mobile_lcdc_chan_cfg;
struct device;
+struct clk;
/*
* flags format
struct sh_mobile_lcdc_chan_cfg *lcd_chan;
struct device *lcd_dev;
unsigned int flags;
+ long (*clk_optimize_parent)(unsigned long target, unsigned long *best_freq,
+ unsigned long *parent_freq);
};
#endif
projects / linux-beck.git / commitdiff