ENGR00275034-2 ARM: dts: add csi and v4l2 capture support on imx6sl-evk

Add CSI module and v4l2 capture support on imx6sl-evk board

Note: CSI has pin conflict with EPDC on imx6sl-evk board.
To use CSI, we can use 'fdt' command in U-Boot to disable EPDC:

fdt addr ${fdt_addr}
fdt set /soc/aips-bus@02000000/epdc@020f4000 status disable

Signed-off-by: Robby Cai <R63905@freescale.com>

diff --git a/arch/arm/boot/dts/imx6sl-evk.dts b/arch/arm/boot/dts/imx6sl-evk.dts
index 02f0f14d21d4be2a3703bf308e2ff34bf2a8eeed..a8fe9fb5e13b20de7d318edbcc5e3ed9448221d9 100644 (file)
--- a/arch/arm/boot/dts/imx6sl-evk.dts
+++ b/arch/arm/boot/dts/imx6sl-evk.dts
@@ -90,6 +90,11 @@
                default-brightness-level = <6>;
        };
 
+       csi_v4l2_cap {
+               compatible = "fsl,imx6sl-csi-v4l2";
+               status = "okay";
+       };
+
        pxp_v4l2_out {
                compatible = "fsl,imx6sl-pxp-v4l2";
                status = "okay";
@@ -142,6 +147,10 @@
                                <24000000>;
 };
 
+&csi {
+       status = "okay";
+};
+
 &cpu0 {
        arm-supply = <&sw1a_reg>;
        soc-supply = <&sw1c_reg>;
@@ -712,6 +721,27 @@
                                MX6SL_PAD_SD3_DAT3__SD3_DATA3           0x170f9
                        >;
                };
+
+               pinctrl_csi_0: csigrp-0 {
+                       fsl,pins = <
+                               MX6SL_PAD_EPDC_GDRL__CSI_MCLK   0x110b0
+                               MX6SL_PAD_EPDC_GDCLK__CSI_PIXCLK 0x110b0
+                               MX6SL_PAD_EPDC_GDSP__CSI_VSYNC  0x110b0
+                               MX6SL_PAD_EPDC_GDOE__CSI_HSYNC  0x110b0
+                               MX6SL_PAD_EPDC_SDLE__CSI_DATA09 0x110b0
+                               MX6SL_PAD_EPDC_SDCLK__CSI_DATA08 0x110b0
+                               MX6SL_PAD_EPDC_D7__CSI_DATA07   0x110b0
+                               MX6SL_PAD_EPDC_D6__CSI_DATA06   0x110b0
+                               MX6SL_PAD_EPDC_D5__CSI_DATA05   0x110b0
+                               MX6SL_PAD_EPDC_D4__CSI_DATA04   0x110b0
+                               MX6SL_PAD_EPDC_D3__CSI_DATA03   0x110b0
+                               MX6SL_PAD_EPDC_D2__CSI_DATA02   0x110b0
+                               MX6SL_PAD_EPDC_D1__CSI_DATA01   0x110b0
+                               MX6SL_PAD_EPDC_D0__CSI_DATA00   0x110b0
+                               MX6SL_PAD_EPDC_SDSHR__GPIO1_IO26 0x80000000
+                               MX6SL_PAD_EPDC_SDOE__GPIO1_IO25  0x80000000
+                       >;
+               };
        };
 };
 

diff --git a/arch/arm/boot/dts/imx6sl.dtsi b/arch/arm/boot/dts/imx6sl.dtsi
index cf098ab2d567ca2ae7db7254e5c6688cd8c442e7..c8b5bbae589dd742e6443d6cb271bdad87897a48 100644 (file)
--- a/arch/arm/boot/dts/imx6sl.dtsi
+++ b/arch/arm/boot/dts/imx6sl.dtsi
@@ -632,8 +632,10 @@
                        };
 
                        csi: csi@020e4000 {
+                               compatible = "fsl,imx6sl-csi";
                                reg = <0x020e4000 0x4000>;
                                interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;
+                               status = "disabled";
                        };
 
                        spdc: spdc@020e8000 {