clk: qcom: Add support for msm8974 RPM-SMD clocks

Add support for the RPM clock controller found on msm8974-based
platforms.

Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org>

diff --git a/Documentation/devicetree/bindings/clock/qcom,rpmcc.txt b/Documentation/devicetree/bindings/clock/qcom,rpmcc.txt
index 7f7ce1f042fd84055f736c37a0440e4ca368a47e..025a42a4d164a049c93bc30446b45ee6cbc15dc8 100644 (file)
--- a/Documentation/devicetree/bindings/clock/qcom,rpmcc.txt
+++ b/Documentation/devicetree/bindings/clock/qcom,rpmcc.txt
@@ -11,6 +11,7 @@ Required properties :
                compatible "qcom,rpmcc" should be also included.
 
                        "qcom,rpmcc-msm8916", "qcom,rpmcc"
+                       "qcom,rpmcc-msm8974", "qcom,rpmcc"
                        "qcom,rpmcc-apq8064", "qcom,rpmcc"
 
 - #clock-cells : shall contain 1

diff --git a/drivers/clk/qcom/clk-smd-rpm.c b/drivers/clk/qcom/clk-smd-rpm.c
index a9ff7020ed151735139798f070a4483f849ac9d0..447b48947beabb2ec60b1641e35bf0ce23610080 100644 (file)
--- a/drivers/clk/qcom/clk-smd-rpm.c
+++ b/drivers/clk/qcom/clk-smd-rpm.c
@@ -327,8 +327,85 @@ static const struct rpm_smd_clk_desc rpm_clk_msm8916 = {
        .num_clks = ARRAY_SIZE(msm8916_clks),
 };
 
+/* msm8974 */
+DEFINE_CLK_SMD_RPM(msm8974, pnoc_clk, pnoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 0);
+DEFINE_CLK_SMD_RPM(msm8974, snoc_clk, snoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 1);
+DEFINE_CLK_SMD_RPM(msm8974, cnoc_clk, cnoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 2);
+DEFINE_CLK_SMD_RPM(msm8974, mmssnoc_ahb_clk, mmssnoc_ahb_a_clk, QCOM_SMD_RPM_BUS_CLK, 3);
+DEFINE_CLK_SMD_RPM(msm8974, bimc_clk, bimc_a_clk, QCOM_SMD_RPM_MEM_CLK, 0);
+DEFINE_CLK_SMD_RPM(msm8974, ocmemgx_clk, ocmemgx_a_clk, QCOM_SMD_RPM_MEM_CLK, 2);
+DEFINE_CLK_SMD_RPM(msm8974, gfx3d_clk_src, gfx3d_a_clk_src, QCOM_SMD_RPM_MEM_CLK, 1);
+DEFINE_CLK_SMD_RPM_BRANCH(msm8974, cxo_clk_src, cxo_a_clk_src, QCOM_SMD_RPM_MISC_CLK, 0, 19200000);
+DEFINE_CLK_SMD_RPM_QDSS(msm8974, qdss_clk, qdss_a_clk, QCOM_SMD_RPM_MISC_CLK, 1);
+DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8974, cxo_d0, cxo_d0_a, 1);
+DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8974, cxo_d1, cxo_d1_a, 2);
+DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8974, cxo_a0, cxo_a0_a, 4);
+DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8974, cxo_a1, cxo_a1_a, 5);
+DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8974, cxo_a2, cxo_a2_a, 6);
+DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8974, div_clk1, div_a_clk1, 11);
+DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8974, div_clk2, div_a_clk2, 12);
+DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8974, diff_clk, diff_a_clk, 7);
+DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8974, cxo_d0_pin, cxo_d0_a_pin, 1);
+DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8974, cxo_d1_pin, cxo_d1_a_pin, 2);
+DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8974, cxo_a0_pin, cxo_a0_a_pin, 4);
+DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8974, cxo_a1_pin, cxo_a1_a_pin, 5);
+DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8974, cxo_a2_pin, cxo_a2_a_pin, 6);
+
+static struct clk_smd_rpm *msm8974_clks[] = {
+       [RPM_CXO_CLK_SRC]       = &msm8974_cxo_clk_src,
+       [RPM_CXO_A_CLK_SRC]     = &msm8974_cxo_a_clk_src,
+       [RPM_PNOC_CLK]          = &msm8974_pnoc_clk,
+       [RPM_PNOC_A_CLK]        = &msm8974_pnoc_a_clk,
+       [RPM_SNOC_CLK]          = &msm8974_snoc_clk,
+       [RPM_SNOC_A_CLK]        = &msm8974_snoc_a_clk,
+       [RPM_BIMC_CLK]          = &msm8974_bimc_clk,
+       [RPM_BIMC_A_CLK]        = &msm8974_bimc_a_clk,
+       [RPM_QDSS_CLK]          = &msm8974_qdss_clk,
+       [RPM_QDSS_A_CLK]        = &msm8974_qdss_a_clk,
+       [RPM_CNOC_CLK]          = &msm8974_cnoc_clk,
+       [RPM_CNOC_A_CLK]        = &msm8974_cnoc_a_clk,
+       [RPM_MMSSNOC_AHB_CLK]   = &msm8974_mmssnoc_ahb_clk,
+       [RPM_MMSSNOC_AHB_A_CLK] = &msm8974_mmssnoc_ahb_a_clk,
+       [RPM_OCMEMGX_CLK]       = &msm8974_ocmemgx_clk,
+       [RPM_OCMEMGX_A_CLK]     = &msm8974_ocmemgx_a_clk,
+       [RPM_GFX3D_CLK_SRC]     = &msm8974_gfx3d_clk_src,
+       [RPM_GFX3D_A_CLK_SRC]   = &msm8974_gfx3d_a_clk_src,
+       [RPM_CXO_D0]            = &msm8974_cxo_d0,
+       [RPM_CXO_D0_A]          = &msm8974_cxo_d0_a,
+       [RPM_CXO_D1]            = &msm8974_cxo_d1,
+       [RPM_CXO_D1_A]          = &msm8974_cxo_d1_a,
+       [RPM_CXO_A0]            = &msm8974_cxo_a0,
+       [RPM_CXO_A0_A]          = &msm8974_cxo_a0_a,
+       [RPM_CXO_A1]            = &msm8974_cxo_a1,
+       [RPM_CXO_A1_A]          = &msm8974_cxo_a1_a,
+       [RPM_CXO_A2]            = &msm8974_cxo_a2,
+       [RPM_CXO_A2_A]          = &msm8974_cxo_a2_a,
+       [RPM_DIV_CLK1]          = &msm8974_div_clk1,
+       [RPM_DIV_A_CLK1]        = &msm8974_div_a_clk1,
+       [RPM_DIV_CLK2]          = &msm8974_div_clk2,
+       [RPM_DIV_A_CLK2]        = &msm8974_div_a_clk2,
+       [RPM_DIFF_CLK]          = &msm8974_diff_clk,
+       [RPM_DIFF_A_CLK]        = &msm8974_diff_a_clk,
+       [RPM_CXO_D0_PIN]        = &msm8974_cxo_d0_pin,
+       [RPM_CXO_D0_A_PIN]      = &msm8974_cxo_d0_a_pin,
+       [RPM_CXO_D1_PIN]        = &msm8974_cxo_d1_pin,
+       [RPM_CXO_D1_A_PIN]      = &msm8974_cxo_d1_a_pin,
+       [RPM_CXO_A0_PIN]        = &msm8974_cxo_a0_pin,
+       [RPM_CXO_A0_A_PIN]      = &msm8974_cxo_a0_a_pin,
+       [RPM_CXO_A1_PIN]        = &msm8974_cxo_a1_pin,
+       [RPM_CXO_A1_A_PIN]      = &msm8974_cxo_a1_a_pin,
+       [RPM_CXO_A2_PIN]        = &msm8974_cxo_a2_pin,
+       [RPM_CXO_A2_A_PIN]      = &msm8974_cxo_a2_a_pin,
+};
+
+static const struct rpm_smd_clk_desc rpm_clk_msm8974 = {
+       .clks = msm8974_clks,
+       .num_clks = ARRAY_SIZE(msm8974_clks),
+};
+
 static const struct of_device_id rpm_smd_clk_match_table[] = {
        { .compatible = "qcom,rpmcc-msm8916", .data = &rpm_clk_msm8916},
+       { .compatible = "qcom,rpmcc-msm8974", .data = &rpm_clk_msm8974},
        { }
 };
 MODULE_DEVICE_TABLE(of, rpm_smd_clk_match_table);

diff --git a/include/dt-bindings/clock/qcom,rpmcc.h b/include/dt-bindings/clock/qcom,rpmcc.h
index 7800ab465d4848ebdf3c2f22a9a9e3f44375fc46..a536ed40cfcccb0516d487327ac05891ceed6a7f 100644 (file)
--- a/include/dt-bindings/clock/qcom,rpmcc.h
+++ b/include/dt-bindings/clock/qcom,rpmcc.h
@@ -42,4 +42,50 @@
 #define RPM_RF_CLK2_PIN                                24
 #define RPM_RF_CLK2_A_PIN                      25
 
+/* msm8974 */
+#define RPM_CXO_CLK_SRC                                0
+#define RPM_CXO_A_CLK_SRC                      1
+#define RPM_PNOC_CLK                           2
+#define RPM_PNOC_A_CLK                         3
+#define RPM_SNOC_CLK                           4
+#define RPM_SNOC_A_CLK                         5
+#define RPM_BIMC_CLK                           6
+#define RPM_BIMC_A_CLK                         7
+#define RPM_QDSS_CLK                           8
+#define RPM_QDSS_A_CLK                         9
+#define RPM_CXO_D0                             10
+#define RPM_CXO_D0_A                           11
+#define RPM_CXO_D1                             12
+#define RPM_CXO_D1_A                           13
+#define RPM_CXO_A0                             14
+#define RPM_CXO_A0_A                           15
+#define RPM_CXO_A1                             16
+#define RPM_CXO_A1_A                           17
+#define RPM_CXO_A2                             18
+#define RPM_CXO_A2_A                           19
+#define RPM_CXO_D0_PIN                         20
+#define RPM_CXO_D0_A_PIN                       21
+#define RPM_CXO_A2_PIN                         22
+#define RPM_CXO_A2_A_PIN                       23
+#define RPM_CXO_A1_PIN                         24
+#define RPM_CXO_A1_A_PIN                       25
+#define RPM_DIFF_CLK                           26
+#define RPM_DIFF_A_CLK                         27
+#define RPM_CNOC_CLK                           28
+#define RPM_CNOC_A_CLK                         29
+#define RPM_MMSSNOC_AHB_CLK                    30
+#define RPM_MMSSNOC_AHB_A_CLK                  31
+#define RPM_OCMEMGX_CLK                                32
+#define RPM_OCMEMGX_A_CLK                      33
+#define RPM_GFX3D_CLK_SRC                      34
+#define RPM_GFX3D_A_CLK_SRC                    35
+#define RPM_DIV_CLK1                           36
+#define RPM_DIV_A_CLK1                         37
+#define RPM_DIV_CLK2                           38
+#define RPM_DIV_A_CLK2                         39
+#define RPM_CXO_D1_PIN                         40
+#define RPM_CXO_D1_A_PIN                       41
+#define RPM_CXO_A0_PIN                         42
+#define RPM_CXO_A0_A_PIN                       43
+
 #endif