MX6Q desclare dma memory bufferable, which cause sdma
load context failed in 60% possibility.
To fix it, we need to add dsb to flush write buffer before
start dma transfer.
Signed-off-by: Zeng Zhaoming <b32542@freescale.com>
init_completion(&sdmac->done);
+ wmb();
__raw_writel(1 << channel, sdma->regs + SDMA_H_START);
ret = wait_for_completion_timeout(&sdmac->done, HZ);
static void sdma_enable_channel(struct sdma_engine *sdma, int channel)
{
+ wmb();
__raw_writel(1 << channel, sdma->regs + SDMA_H_START);
}