**/
int lis3l02dq_spi_write_reg_8(struct iio_dev *indio_dev,
u8 reg_address,
- u8 *val)
+ u8 val)
{
int ret;
struct lis3l02dq_state *st = iio_priv(indio_dev);
mutex_lock(&st->buf_lock);
st->tx[0] = LIS3L02DQ_WRITE_REG(reg_address);
- st->tx[1] = *val;
+ st->tx[1] = val;
ret = spi_write(st->us, st->tx, 2);
mutex_unlock(&st->buf_lock);
return -EINVAL;
sval = val;
reg = lis3l02dq_axis_map[LIS3L02DQ_BIAS][chan->address];
- ret = lis3l02dq_spi_write_reg_8(indio_dev, reg, (u8 *)&sval);
+ ret = lis3l02dq_spi_write_reg_8(indio_dev, reg, sval);
break;
case (1 << IIO_CHAN_INFO_CALIBSCALE_SEPARATE):
if (val & ~0xFF)
return -EINVAL;
uval = val;
reg = lis3l02dq_axis_map[LIS3L02DQ_GAIN][chan->address];
- ret = lis3l02dq_spi_write_reg_8(indio_dev, reg, &uval);
+ ret = lis3l02dq_spi_write_reg_8(indio_dev, reg, uval);
break;
}
return ret;
ret = lis3l02dq_spi_write_reg_8(indio_dev,
LIS3L02DQ_REG_CTRL_1_ADDR,
- &t);
+ t);
error_ret_mutex:
mutex_unlock(&indio_dev->mlock);
/* Write suitable defaults to ctrl1 */
ret = lis3l02dq_spi_write_reg_8(indio_dev,
LIS3L02DQ_REG_CTRL_1_ADDR,
- &val);
+ val);
if (ret) {
dev_err(&st->us->dev, "problem with setup control register 1");
goto err_ret;
/* Repeat as sometimes doesn't work first time?*/
ret = lis3l02dq_spi_write_reg_8(indio_dev,
LIS3L02DQ_REG_CTRL_1_ADDR,
- &val);
+ val);
if (ret) {
dev_err(&st->us->dev, "problem with setup control register 1");
goto err_ret;
val = LIS3L02DQ_DEFAULT_CTRL2;
ret = lis3l02dq_spi_write_reg_8(indio_dev,
LIS3L02DQ_REG_CTRL_2_ADDR,
- &val);
+ val);
if (ret) {
dev_err(&st->us->dev, "problem with setup control register 2");
goto err_ret;
val = LIS3L02DQ_REG_WAKE_UP_CFG_LATCH_SRC;
ret = lis3l02dq_spi_write_reg_8(indio_dev,
LIS3L02DQ_REG_WAKE_UP_CFG_ADDR,
- &val);
+ val);
if (ret)
dev_err(&st->us->dev, "problem with interrupt cfg register");
err_ret:
control &= ~LIS3L02DQ_REG_CTRL_2_ENABLE_INTERRUPT;
ret = lis3l02dq_spi_write_reg_8(indio_dev,
LIS3L02DQ_REG_CTRL_2_ADDR,
- &control);
+ control);
if (ret)
goto error_ret;
/* Also for consistency clear the mask */
ret = lis3l02dq_spi_write_reg_8(indio_dev,
LIS3L02DQ_REG_WAKE_UP_CFG_ADDR,
- &val);
+ val);
if (ret)
goto error_ret;
if (changed) {
ret = lis3l02dq_spi_write_reg_8(indio_dev,
LIS3L02DQ_REG_WAKE_UP_CFG_ADDR,
- &val);
+ val);
if (ret)
goto error_ret;
control = val & 0x3f ?
(control & ~LIS3L02DQ_REG_CTRL_2_ENABLE_INTERRUPT);
ret = lis3l02dq_spi_write_reg_8(indio_dev,
LIS3L02DQ_REG_CTRL_2_ADDR,
- &control);
+ control);
if (ret)
goto error_ret;
}
mutex_lock(&indio_dev->mlock);
ret = lis3l02dq_spi_write_reg_8(indio_dev,
LIS3L02DQ_REG_CTRL_1_ADDR,
- &val);
+ val);
if (ret) {
dev_err(&st->us->dev, "problem with turning device off: ctrl1");
goto err_ret;
ret = lis3l02dq_spi_write_reg_8(indio_dev,
LIS3L02DQ_REG_CTRL_2_ADDR,
- &val);
+ val);
if (ret)
dev_err(&st->us->dev, "problem with turning device off: ctrl2");
err_ret:
/* The double write is to overcome a hardware bug?*/
ret = lis3l02dq_spi_write_reg_8(indio_dev,
LIS3L02DQ_REG_CTRL_2_ADDR,
- &valold);
+ valold);
if (ret)
goto error_ret;
ret = lis3l02dq_spi_write_reg_8(indio_dev,
LIS3L02DQ_REG_CTRL_2_ADDR,
- &valold);
+ valold);
if (ret)
goto error_ret;
st->trigger_on = false;
st->trigger_on = true;
ret = lis3l02dq_spi_write_reg_8(indio_dev,
LIS3L02DQ_REG_CTRL_2_ADDR,
- &valold);
+ valold);
if (ret)
goto error_ret;
}
return -EINVAL;
ret = lis3l02dq_spi_write_reg_8(indio_dev,
LIS3L02DQ_REG_CTRL_1_ADDR,
- &t);
+ t);
if (ret)
goto error_ret;
ret = lis3l02dq_spi_write_reg_8(indio_dev,
LIS3L02DQ_REG_CTRL_1_ADDR,
- &t);
+ t);
error_ret:
return ret;