clk: lpc32xx: add HCLK PLL output configuration

This patch add the support to setup the HCLK PLL output
using the "assigned-clock-rates" parameter in the device tree.

If the option is not use, the clock setup by the kickstart
and/or bootloader remain unchanged.

The previous kernel version did not change the clock frequency
output setup by the kickstart and/or bootloader;
this version always setup the clock frequency output to 208MHz.

Signed-off-by: Sylvain Lemieux <slemieux@tycoint.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>

diff --git a/drivers/clk/nxp/clk-lpc32xx.c b/drivers/clk/nxp/clk-lpc32xx.c
index 981ff0dd88b4a2f929e659b8c0bcb9f2c26a3d49..48b3a11aa09a9e48bd962528eef69ae06c8c6022 100644 (file)
--- a/drivers/clk/nxp/clk-lpc32xx.c
+++ b/drivers/clk/nxp/clk-lpc32xx.c
@@ -87,7 +87,7 @@ enum {
 
 enum {
        /* Start from the last defined clock in dt bindings */
-       LPC32XX_CLK_ADC_DIV = LPC32XX_CLK_ADC + 1,
+       LPC32XX_CLK_ADC_DIV = LPC32XX_CLK_HCLK_PLL + 1,
        LPC32XX_CLK_ADC_RTC,
        LPC32XX_CLK_TEST1,
        LPC32XX_CLK_TEST2,
@@ -96,7 +96,6 @@ enum {
        LPC32XX_CLK_OSC,
        LPC32XX_CLK_SYS,
        LPC32XX_CLK_PLL397X,
-       LPC32XX_CLK_HCLK_PLL,
        LPC32XX_CLK_HCLK_DIV_PERIPH,
        LPC32XX_CLK_HCLK_DIV,
        LPC32XX_CLK_HCLK,
@@ -1526,9 +1525,6 @@ static void __init lpc32xx_clk_init(struct device_node *np)
 
        of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
 
-       /* For 13MHz osc valid output range of PLL is from 156MHz to 266.5MHz */
-       clk_set_rate(clk[LPC32XX_CLK_HCLK_PLL], 208000000);
-
        /* Set 48MHz rate of USB PLL clock */
        clk_set_rate(clk[LPC32XX_CLK_USB_PLL], 48000000);
 

diff --git a/include/dt-bindings/clock/lpc32xx-clock.h b/include/dt-bindings/clock/lpc32xx-clock.h
index bcb1c9a7351958bb8ba1c76be27dffeb32bd23a0..d41b6fea145079d0da22a5d195ab7f001e7335a7 100644 (file)
--- a/include/dt-bindings/clock/lpc32xx-clock.h
+++ b/include/dt-bindings/clock/lpc32xx-clock.h
@@ -47,6 +47,7 @@
 #define LPC32XX_CLK_PWM1       32
 #define LPC32XX_CLK_PWM2       33
 #define LPC32XX_CLK_ADC                34
+#define LPC32XX_CLK_HCLK_PLL   35
 
 /* LPC32XX USB clocks */
 #define LPC32XX_USB_CLK_I2C    1