ENGR00141363 ARM imx53 clock: change di0 clock default parent to pll3

If enable both LVDS and one display device use external di clock, there will
be conflict between their clock parent -- both use pll4 on mx53. So it need
change di0 clock parent to pll3, and then uart parent need change to pll2 to
avoid console mess.

Signed-off-by: Jason Chen <b02280@freescale.com>

diff --git a/arch/arm/mach-mx5/clock.c b/arch/arm/mach-mx5/clock.c
index c540f08292f0dfa46734def16719d69c97400cd0..64209fc437acdbaf3a75f7ba261ee6b7c67830ce 100755 (executable)
--- a/arch/arm/mach-mx5/clock.c
+++ b/arch/arm/mach-mx5/clock.c
@@ -5036,8 +5036,6 @@ int __init mx53_clocks_init(unsigned long ckil, unsigned long osc, unsigned long
        clk_set_parent(&esdhc2_clk[0], &esdhc1_clk[0]);
        clk_set_parent(&esdhc3_clk[0], &pll2_sw_clk);
 
-       clk_set_parent(&ipu_di_clk[0], &pll4_sw_clk);
-
 #if 0
        /*Setup the LPM bypass bits */
        reg = __raw_readl(MXC_CCM_CLPCR);
@@ -5146,7 +5144,6 @@ int __init mx53_clocks_init(unsigned long ckil, unsigned long osc, unsigned long
 
        clk_set_parent(&arm_axi_clk, &axi_b_clk);
        clk_set_parent(&ipu_clk[0], &axi_b_clk);
-       clk_set_parent(&uart_main_clk, &pll3_sw_clk);
        clk_set_parent(&gpu3d_clk, &axi_b_clk);
        clk_set_parent(&gpu2d_clk, &axi_b_clk);