ARC: [dts] Introduce Timer bindings

ARC Timers have historically been probed directly.
As precursor to start probing Timers thru DT introduce these bindings
Note that to keep series bisectable, these bindings are not yet used in
code.

Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
Cc: devicetree@vger.kernel.org
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>

diff --git a/Documentation/devicetree/bindings/timer/snps,arc-timer.txt b/Documentation/devicetree/bindings/timer/snps,arc-timer.txt
new file mode 100644 (file)
index 0000000..4ef0246
--- /dev/null
+++ b/Documentation/devicetree/bindings/timer/snps,arc-timer.txt
@@ -0,0 +1,31 @@
+Synopsys ARC Local Timer with Interrupt Capabilities
+- Found on all ARC CPUs (ARC700/ARCHS)
+- Can be optionally programmed to interrupt on Limit
+- Two idential copies TIMER0 and TIMER1 exist in ARC cores and historically
+  TIMER0 used as clockevent provider (true for all ARC cores)
+  TIMER1 used for clocksource (mandatory for ARC700, optional for ARC HS)
+
+Required properties:
+
+- compatible : should be "snps,arc-timer"
+- interrupts : single Interrupt going into parent intc
+              (16 for ARCHS cores, 3 for ARC700 cores)
+- clocks     : phandle to the source clock
+
+Optional properties:
+
+- interrupt-parent : phandle to parent intc
+
+Example:
+
+       timer0 {
+               compatible = "snps,arc-timer";
+               interrupts = <3>;
+               interrupt-parent = <&core_intc>;
+               clocks = <&core_clk>;
+       };
+
+       timer1 {
+               compatible = "snps,arc-timer";
+               clocks = <&core_clk>;
+       };

diff --git a/Documentation/devicetree/bindings/timer/snps,archs-gfrc.txt b/Documentation/devicetree/bindings/timer/snps,archs-gfrc.txt
new file mode 100644 (file)
index 0000000..b6cd1b3
--- /dev/null
+++ b/Documentation/devicetree/bindings/timer/snps,archs-gfrc.txt
@@ -0,0 +1,14 @@
+Synopsys ARC Free Running 64-bit Global Timer for ARC HS CPUs
+- clocksource provider for SMP SoC
+
+Required properties:
+
+- compatible : should be "snps,archs-gfrc"
+- clocks     : phandle to the source clock
+
+Example:
+
+       gfrc {
+               compatible = "snps,archs-gfrc";
+               clocks = <&core_clk>;
+       };

diff --git a/Documentation/devicetree/bindings/timer/snps,archs-rtc.txt b/Documentation/devicetree/bindings/timer/snps,archs-rtc.txt
new file mode 100644 (file)
index 0000000..47bd7a7
--- /dev/null
+++ b/Documentation/devicetree/bindings/timer/snps,archs-rtc.txt
@@ -0,0 +1,14 @@
+Synopsys ARC Free Running 64-bit Local Timer for ARC HS CPUs
+- clocksource provider for UP SoC
+
+Required properties:
+
+- compatible : should be "snps,archs-rtc"
+- clocks     : phandle to the source clock
+
+Example:
+
+       rtc {
+               compatible = "snps,arc-rtc";
+               clocks = <&core_clk>;
+       };

diff --git a/arch/arc/boot/dts/abilis_tb10x.dtsi b/arch/arc/boot/dts/abilis_tb10x.dtsi
index cfb5052239a1cffdcb3f8ac3dc07537441d55bef..663671f2268042ba85183b74c1feea84f92cc42a 100644 (file)
--- a/arch/arc/boot/dts/abilis_tb10x.dtsi
+++ b/arch/arc/boot/dts/abilis_tb10x.dtsi
@@ -35,6 +35,20 @@
                };
        };
 
+       /* TIMER0 with interrupt for clockevent */
+       timer0 {
+               compatible = "snps,arc-timer";
+               interrupts = <3>;
+               interrupt-parent = <&intc>;
+               clocks = <&cpu_clk>;
+       };
+
+       /* TIMER1 for free running clocksource */
+       timer1 {
+               compatible = "snps,arc-timer";
+               clocks = <&cpu_clk>;
+       };
+
        soc100 {
                #address-cells  = <1>;
                #size-cells     = <1>;

diff --git a/arch/arc/boot/dts/skeleton.dtsi b/arch/arc/boot/dts/skeleton.dtsi
index 296d371a335c8374b98efba984d95b705b3f343b..3a10cc633e2b0e200b8eacfd16ff99e56a718652 100644 (file)
--- a/arch/arc/boot/dts/skeleton.dtsi
+++ b/arch/arc/boot/dts/skeleton.dtsi
@@ -30,6 +30,20 @@
                };
        };
 
+       /* TIMER0 with interrupt for clockevent */
+       timer0 {
+               compatible = "snps,arc-timer";
+               interrupts = <3>;
+               interrupt-parent = <&core_intc>;
+               clocks = <&core_clk>;
+       };
+
+       /* TIMER1 for free running clocksource */
+       timer1 {
+               compatible = "snps,arc-timer";
+               clocks = <&core_clk>;
+       };
+
        memory {
                device_type = "memory";
                reg = <0x80000000 0x10000000>;  /* 256M */

diff --git a/arch/arc/boot/dts/skeleton_hs.dtsi b/arch/arc/boot/dts/skeleton_hs.dtsi
index a53876669030f4768cff95f3237d9952b9392b35..71fd308a9298aac6435d67e6863314d26e140396 100644 (file)
--- a/arch/arc/boot/dts/skeleton_hs.dtsi
+++ b/arch/arc/boot/dts/skeleton_hs.dtsi
@@ -25,6 +25,26 @@
                };
        };
 
+       /* TIMER0 with interrupt for clockevent */
+       timer0 {
+               compatible = "snps,arc-timer";
+               interrupts = <16>;
+               interrupt-parent = <&core_intc>;
+               clocks = <&core_clk>;
+       };
+
+       /* 64-bit Local RTC: preferred clocksource for UP */
+       rtc {
+               compatible = "snps,archs-timer-rtc";
+               clocks = <&core_clk>;
+       };
+
+       /* TIMER1 for free running clocksource: Fallback if rtc not found */
+       timer1 {
+               compatible = "snps,arc-timer";
+               clocks = <&core_clk>;
+       };
+
        memory {
                device_type = "memory";
                reg = <0x80000000 0x10000000>;  /* 256M */

diff --git a/arch/arc/boot/dts/skeleton_hs_idu.dtsi b/arch/arc/boot/dts/skeleton_hs_idu.dtsi
index 74898d017f7ac552e2c86f82ac34265d5b124992..d1cb25a6698952b461925d5a361223c8bc3c5080 100644 (file)
--- a/arch/arc/boot/dts/skeleton_hs_idu.dtsi
+++ b/arch/arc/boot/dts/skeleton_hs_idu.dtsi
@@ -25,6 +25,20 @@
                };
        };
 
+       /* TIMER0 with interrupt for clockevent */
+       timer0 {
+               compatible = "snps,arc-timer";
+               interrupts = <16>;
+               interrupt-parent = <&core_intc>;
+               clocks = <&core_clk>;
+       };
+
+       /* 64-bit Global Free Running Counter */
+       gfrc {
+               compatible = "snps,archs-timer-gfrc";
+               clocks = <&core_clk>;
+       };
+
        memory {
                device_type = "memory";
                reg = <0x80000000 0x10000000>;  /* 256M */