#include <linux/gpio.h>
#include <linux/regulator/machine.h>
#include <linux/mfd/pfuze.h>
+#include <linux/io.h>
#include <mach/irqs.h>
+#include "crm_regs.h"
+#include "regs-anadig.h"
+#include "cpu_op-mx6.h"
/*
* Convenience conversion.
/* 7-bit I2C bus slave address */
#define PFUZE100_I2C_ADDR (0x08)
/*SWBST*/
+#define PFUZE100_SW1AVOL 32
+#define PFUZE100_SW1AVOL_VSEL_M (0x3f<<0)
+#define PFUZE100_SW1CVOL 46
+#define PFUZE100_SW1CVOL_VSEL_M (0x3f<<0)
#define PFUZE100_SW1ASTANDBY 33
#define PFUZE100_SW1ASTANDBY_STBY_VAL (0x18)
#define PFUZE100_SW1ASTANDBY_STBY_M (0x3f<<0)
#define PFUZE100_SWBSTCON1_SWBSTMOD_VAL (0x1<<2)
#define PFUZE100_SWBSTCON1_SWBSTMOD_M (0x3<<2)
+extern u32 arm_max_freq;
#ifdef CONFIG_MX6_INTER_LDO_BYPASS
static struct regulator_consumer_supply sw1_consumers[] = {
static int pfuze100_init(struct mc_pfuze *pfuze)
{
int ret;
+ unsigned int reg;
+ if (arm_max_freq == CPU_AT_1_2GHz) {
+ /*VDDARM_IN 1.425V*/
+ ret = pfuze_reg_rmw(pfuze, PFUZE100_SW1AVOL,
+ PFUZE100_SW1AVOL_VSEL_M,
+ 0x2d);
+ if (ret)
+ goto err;
+ /*VDDSOC_IN 1.425V*/
+ ret = pfuze_reg_rmw(pfuze, PFUZE100_SW1CVOL,
+ PFUZE100_SW1CVOL_VSEL_M,
+ 0x2d);
+ if (ret)
+ goto err;
+ /*set VDDSOC&VDDPU to 1.25V*/
+ reg = __raw_readl(ANADIG_REG_CORE);
+ reg &= ~BM_ANADIG_REG_CORE_REG2_TRG;
+ reg |= BF_ANADIG_REG_CORE_REG2_TRG(0x16);
+ reg &= ~BM_ANADIG_REG_CORE_REG1_TRG;
+ reg |= BF_ANADIG_REG_CORE_REG1_TRG(0x16);
+ __raw_writel(reg, ANADIG_REG_CORE);
+
+ }
ret = pfuze_reg_rmw(pfuze, PFUZE100_SW1ASTANDBY,
PFUZE100_SW1ASTANDBY_STBY_M,
PFUZE100_SW1ASTANDBY_STBY_VAL);