arm: socfpga: Add Cadence QSPI support to config header

With this driver enabled for SoCFPGA, access to SPI NOR flash is
supported.

The configuration (page size, timing info) will be taken from the
DT. See socrates as an example.

This QSPI supports depends on DT. So QSPI is only enabled if
CONFIG_OF_CONTROL is defined (see socfpga_socrates_defconfig).

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Vince Bridgers <vbridger@altera.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Pavel Machek <pavel@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>

diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h
index c4ac94d0eb302ec6c64193fc99f109f069b00de8..2b7534b936232ed17a74bc0135e3ca340f4e31ee 100644 (file)
--- a/include/configs/socfpga_common.h
+++ b/include/configs/socfpga_common.h
@@ -159,7 +159,7 @@
 #define CONFIG_SYS_MMC_MAX_BLK_COUNT   256     /* FIXME -- SPL only? */
 #endif
 
- /*
+/*
  * I2C support
  */
 #define CONFIG_SYS_I2C
@@ -186,6 +186,29 @@ unsigned int cm_get_l4_sp_clk_hz(void);
 #endif
 #define CONFIG_CMD_I2C
 
+/*
+ * QSPI support
+ */
+#ifdef CONFIG_OF_CONTROL       /* QSPI is controlled via DT */
+#define CONFIG_CMD_DM
+#define CONFIG_DM
+#define CONFIG_DM_SPI
+#define CONFIG_DM_SPI_FLASH
+#define CONFIG_CADENCE_QSPI
+/* Enable multiple SPI NOR flash manufacturers */
+#define CONFIG_SPI_FLASH               /* SPI flash subsystem */
+#define CONFIG_SPI_FLASH_STMICRO       /* Micron/Numonyx flash */
+#define CONFIG_SPI_FLASH_SPANSION      /* Spansion flash */
+#define CONFIG_SPI_FLASH_MTD
+/* QSPI reference clock */
+#ifndef __ASSEMBLY__
+unsigned int cm_get_qspi_controller_clk_hz(void);
+#define CONFIG_CQSPI_REF_CLK           cm_get_qspi_controller_clk_hz()
+#endif
+#define CONFIG_CQSPI_DECODER           0
+#define CONFIG_CMD_SF
+#endif
+
 /*
  * Serial Driver
  */