ARM: tegra: fix pclk rate

Commit 40f9cf0 "ARM: tegra: reparent sclk to pll_c_out1" changed the
rate of hclk. Since pclk is derived from that, and only has integer
dividers, the pclk rate needs to change in the same fashion, from 54MHz
to 60MHz.

Signed-off-by: Stephen Warren <swarren@nvidia.com>

diff --git a/arch/arm/mach-tegra/common.c b/arch/arm/mach-tegra/common.c
index e9690041868223a71ad8dfd7e62f7c8f25b851e0..a4fba8835136fef72cfd9b65100377c7da9fa6ae 100644 (file)
--- a/arch/arm/mach-tegra/common.c
+++ b/arch/arm/mach-tegra/common.c
@@ -87,7 +87,7 @@ static __initdata struct tegra_clk_init_table tegra20_clk_init_table[] = {
        { "pll_c_out1", "pll_c",        120000000,      true },
        { "sclk",       "pll_c_out1",   120000000,      true },
        { "hclk",       "sclk",         120000000,      true },
-       { "pclk",       "hclk",         54000000,       true },
+       { "pclk",       "hclk",         60000000,       true },
        { "csite",      NULL,           0,              true },
        { "emc",        NULL,           0,              true },
        { "cpu",        NULL,           0,              true },