{
struct wdog_regs *regs = (struct wdog_regs *)IMX_WDT_BASE;
/* Disable watchdog and set Time-Out field to 0 */
- writel(0x00000000, ®s->wcr);
+ writew(0x0000, ®s->wcr);
/* Write Service Sequence */
- writel(0x00005555, ®s->wsr);
- writel(0x0000AAAA, ®s->wsr);
+ writew(0x5555, ®s->wsr);
+ writew(0xAAAA, ®s->wsr);
/* Enable watchdog */
- writel(WCR_WDE, ®s->wcr);
+ writew(WCR_WDE, ®s->wcr);
while (1);
/*NOTREACHED*/
config TARGET_EMBESTMX6BOARDS
bool "embestmx6boards"
+config TARGET_GE_B450V3
+ bool "General Electric B450v3"
+ select MX6Q
+
+config TARGET_GE_B650V3
+ bool "General Electric B650v3"
+ select MX6Q
+
+config TARGET_GE_B850V3
+ bool "General Electric B850v3"
+ select MX6Q
+
config TARGET_GW_VENTANA
bool "gw_ventana"
select SUPPORT_SPL
config TARGET_MX6SXSABRESD
bool "mx6sxsabresd"
+ select MX6SX
select SUPPORT_SPL
select DM
select DM_THERMAL
config TARGET_MX6SXSABREAUTO
bool "mx6sxsabreauto"
+ select MX6SX
select DM
select DM_THERMAL
config TARGET_WARP
bool "WaRP"
+config TARGET_XPRESS
+ bool "CCV xPress"
+ select MX6UL
+ select DM
+ select DM_THERMAL
+ select SUPPORT_SPL
+
endchoice
config SYS_SOC
default "mx6"
+source "board/ge/bx50v3/Kconfig"
source "board/aristainetos/Kconfig"
source "board/bachmann/ot1200/Kconfig"
source "board/barco/platinum/Kconfig"
source "board/barco/titanium/Kconfig"
source "board/boundary/nitrogen6x/Kconfig"
+source "board/ccv/xpress/Kconfig"
source "board/compulab/cm_fx6/Kconfig"
source "board/congatec/cgtqmx6eval/Kconfig"
source "board/embest/mx6boards/Kconfig"
printf("PLL_NET %8d MHz\n", freq / 1000000);
printf("\n");
+ printf("ARM %8d kHz\n", mxc_get_clock(MXC_ARM_CLK) / 1000);
printf("IPG %8d kHz\n", mxc_get_clock(MXC_IPG_CLK) / 1000);
printf("UART %8d kHz\n", mxc_get_clock(MXC_UART_CLK) / 1000);
#ifdef CONFIG_MXC_SPI
#include <asm/arch/sys_proto.h>
#include <asm/io.h>
#include <asm/types.h>
+#include <wait_bit.h>
#if defined(CONFIG_MX6QDL) || defined(CONFIG_MX6Q) || defined(CONFIG_MX6D)
-static int wait_for_bit(void *reg, const uint32_t mask, bool set)
-{
- unsigned int timeout = 1000;
- u32 val;
-
- while (--timeout) {
- val = readl(reg);
- if (!set)
- val = ~val;
-
- if ((val & mask) == mask)
- return 0;
-
- udelay(1);
- }
-
- printf("%s: Timeout (reg=%p mask=%08x wait_set=%i)\n",
- __func__, reg, mask, set);
- hang(); /* DRAM couldn't be calibrated, game over :-( */
-}
-
static void reset_read_data_fifos(void)
{
struct mmdc_p_regs *mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR;
/* Reset data FIFOs twice. */
setbits_le32(&mmdc0->mpdgctrl0, 1 << 31);
- wait_for_bit(&mmdc0->mpdgctrl0, 1 << 31, 0);
+ wait_for_bit("MMDC", &mmdc0->mpdgctrl0, 1 << 31, 0, 100, 0);
setbits_le32(&mmdc0->mpdgctrl0, 1 << 31);
- wait_for_bit(&mmdc0->mpdgctrl0, 1 << 31, 0);
+ wait_for_bit("MMDC", &mmdc0->mpdgctrl0, 1 << 31, 0, 100, 0);
}
static void precharge_all(const bool cs0_enable, const bool cs1_enable)
*/
if (cs0_enable) { /* CS0 */
writel(0x04008050, &mmdc0->mdscr);
- wait_for_bit(&mmdc0->mdscr, 1 << 14, 1);
+ wait_for_bit("MMDC", &mmdc0->mdscr, 1 << 14, 1, 100, 0);
}
if (cs1_enable) { /* CS1 */
writel(0x04008058, &mmdc0->mdscr);
- wait_for_bit(&mmdc0->mdscr, 1 << 14, 1);
+ wait_for_bit("MMDC", &mmdc0->mdscr, 1 << 14, 1, 100, 0);
}
}
* 7. Upon completion of this process the MMDC de-asserts
* the MPWLGCR[HW_WL_EN]
*/
- wait_for_bit(&mmdc0->mpwlgcr, 1 << 0, 0);
+ wait_for_bit("MMDC", &mmdc0->mpwlgcr, 1 << 0, 0, 100, 0);
/*
* 8. check for any errors: check both PHYs for x64 configuration,
writel(0x00008028, &mmdc0->mdscr);
/* poll to make sure the con_ack bit was asserted */
- wait_for_bit(&mmdc0->mdscr, 1 << 14, 1);
+ wait_for_bit("MMDC", &mmdc0->mdscr, 1 << 14, 1, 100, 0);
/*
* Check MDMISC register CALIB_PER_CS to see which CS calibration
* this bit until it clears to indicate completion of the write access.
*/
setbits_le32(&mmdc0->mpswdar0, 1);
- wait_for_bit(&mmdc0->mpswdar0, 1 << 0, 0);
+ wait_for_bit("MMDC", &mmdc0->mpswdar0, 1 << 0, 0, 100, 0);
/* Set the RD_DL_ABS# bits to their default values
* (will be calibrated later in the read delay-line calibration).
setbits_le32(&mmdc0->mpdgctrl0, 5 << 28);
/* Poll for completion. MPDGCTRL0[HW_DG_EN] should be 0 */
- wait_for_bit(&mmdc0->mpdgctrl0, 1 << 28, 0);
+ wait_for_bit("MMDC", &mmdc0->mpdgctrl0, 1 << 28, 0, 100, 0);
/*
* Check to see if any errors were encountered during calibration
* setting MPRDDLHWCTL[HW_RD_DL_EN] = 0. Also, ensure that
* no error bits were set.
*/
- wait_for_bit(&mmdc0->mprddlhwctl, 1 << 4, 0);
+ wait_for_bit("MMDC", &mmdc0->mprddlhwctl, 1 << 4, 0, 100, 0);
/* check both PHYs for x64 configuration, if x32, check only PHY0 */
if (readl(&mmdc0->mprddlhwctl) & 0x0000000f)
* by setting MPWRDLHWCTL[HW_WR_DL_EN] = 0.
* Also, ensure that no error bits were set.
*/
- wait_for_bit(&mmdc0->mpwrdlhwctl, 1 << 4, 0);
+ wait_for_bit("MMDC", &mmdc0->mpwrdlhwctl, 1 << 4, 0, 100, 0);
/* Check both PHYs for x64 configuration, if x32, check only PHY0 */
if (readl(&mmdc0->mpwrdlhwctl) & 0x0000000f)
writel(0x0, &mmdc0->mdscr); /* CS0 */
/* Poll to make sure the con_ack bit is clear */
- wait_for_bit(&mmdc0->mdscr, 1 << 14, 0);
+ wait_for_bit("MMDC", &mmdc0->mdscr, 1 << 14, 0, 100, 0);
/*
* Print out the registers that were updated as a result
reg = readl(&mxc_ccm->ccdr);
/* Clear MMDC channel mask */
- reg &= ~(MXC_CCM_CCDR_MMDC_CH1_HS_MASK | MXC_CCM_CCDR_MMDC_CH0_HS_MASK);
+ if (is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL) || is_cpu_type(MXC_CPU_MX6SL))
+ reg &= ~(MXC_CCM_CCDR_MMDC_CH1_HS_MASK);
+ else
+ reg &= ~(MXC_CCM_CCDR_MMDC_CH1_HS_MASK | MXC_CCM_CCDR_MMDC_CH0_HS_MASK);
writel(reg, &mxc_ccm->ccdr);
}
*/
init_bandgap();
- /*
- * When low freq boot is enabled, ROM will not set AHB
- * freq, so we need to ensure AHB freq is 132MHz in such
- * scenario.
- */
- if (mxc_get_clock(MXC_ARM_CLK) == 396000000)
- set_ahb_rate(132000000);
+ if (!IS_ENABLED(CONFIG_MX6UL)) {
+ /*
+ * When low freq boot is enabled, ROM will not set AHB
+ * freq, so we need to ensure AHB freq is 132MHz in such
+ * scenario.
+ *
+ * To i.MX6UL, when power up, default ARM core and
+ * AHB rate is 396M and 132M.
+ */
+ if (mxc_get_clock(MXC_ARM_CLK) == 396000000)
+ set_ahb_rate(132000000);
+ }
+
+ if (IS_ENABLED(CONFIG_MX6UL) && is_soc_rev(CHIP_REV_1_0) == 0) {
+ /*
+ * According to the design team's requirement on i.MX6UL,
+ * the PMIC_STBY_REQ PAD should be configured as open
+ * drain 100K (0x0000b8a0).
+ * Only exists on TO1.0
+ */
+ writel(0x0000b8a0, IOMUXC_BASE_ADDR + 0x29c);
+ }
- /* Set perclk to source from OSC 24MHz */
+ /* Set perclk to source from OSC 24MHz */
#if defined(CONFIG_MX6SL)
set_preclk_from_osc();
#endif
config TARGET_MX7DSABRESD
bool "mx7dsabresd"
+ select MX7D
+ select DM
+ select DM_THERMAL
+
+config TARGET_WARP7
+ bool "warp7"
+ select MX7D
select DM
select DM_THERMAL
default "mx7"
source "board/freescale/mx7dsabresd/Kconfig"
+source "board/warp7/Kconfig"
endif
return val;
}
+static bool is_mx7d(void)
+{
+ struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
+ struct fuse_bank *bank = &ocotp->bank[1];
+ struct fuse_bank1_regs *fuse =
+ (struct fuse_bank1_regs *)bank->fuse_regs;
+ int val;
+
+ val = readl(&fuse->tester4);
+ if (val & 1)
+ return false;
+ else
+ return true;
+}
+
u32 get_cpu_rev(void)
{
struct mxc_ccm_anatop_reg *ccm_anatop = (struct mxc_ccm_anatop_reg *)
u32 reg = readl(&ccm_anatop->digprog);
u32 type = (reg >> 16) & 0xff;
+ if (!is_mx7d())
+ type = MXC_CPU_MX7S;
+
reg &= 0xff;
return (type << 12) | reg;
}
const char *get_imx_type(u32 imxtype)
{
switch (imxtype) {
+ case MXC_CPU_MX7S:
+ return "7SOLO"; /* Single-core version of the mx7 */
case MXC_CPU_MX7D:
return "7D"; /* Dual-core version of the mx7 */
case MXC_CPU_MX6QP:
#define MXC_CPU_MX6D 0x67
#define MXC_CPU_MX6DP 0x68
#define MXC_CPU_MX6QP 0x69
+#define MXC_CPU_MX7S 0x71 /* dummy ID */
#define MXC_CPU_MX7D 0x72
#define MXC_CPU_VF610 0xF6 /* dummy ID */
/* Watchdog Registers*/
struct wdog_regs {
- u32 wcr;
- u32 wsr;
- u32 wstr;
+ u16 wcr;
+ u16 wsr;
+ u16 wstr;
};
/* PLL registers */
#endif
#define UART1_BASE (ATZ1_BASE_ADDR + 0x20000)
#define ESAI1_BASE_ADDR (ATZ1_BASE_ADDR + 0x24000)
+#define UART8_BASE (ATZ1_BASE_ADDR + 0x24000)
#define SSI1_BASE_ADDR (ATZ1_BASE_ADDR + 0x28000)
#define SSI2_BASE_ADDR (ATZ1_BASE_ADDR + 0x2C000)
#define SSI3_BASE_ADDR (ATZ1_BASE_ADDR + 0x30000)
--- /dev/null
+if TARGET_XPRESS
+
+config SYS_BOARD
+ default "xpress"
+
+config SYS_VENDOR
+ default "ccv"
+
+config SYS_CONFIG_NAME
+ default "xpress"
+
+endif
--- /dev/null
+CCV XPRESS BOARD
+M: Stefan Roese <sr@denx.de>
+S: Maintained
+F: board/ccv/xpress/
+F: include/configs/xpress.h
+F: configs/xpress_defconfig
+F: configs/xpress_spl_defconfig
--- /dev/null
+#
+# Copyright (C) 2015-2016 Stefan Roese <sr@denx.de>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := xpress.o
+obj-$(CONFIG_SPL_BUILD) += spl.o
--- /dev/null
+/*
+ * Copyright (C) 2015-2016 Stefan Roese <sr@denx.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * Refer docs/README.imxmage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+
+/* image version */
+
+IMAGE_VERSION 2
+
+/*
+ * Boot Device : one of
+ * sd, nand
+ */
+BOOT_FROM sd
+
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type Address Value
+ *
+ * where:
+ * Addr-type register length (1,2 or 4 bytes)
+ * Address absolute address of the register
+ * value value to be stored in the register
+ */
+
+#define __ASSEMBLY__
+#include <config.h>
+
+/* Enable all clocks */
+DATA 4 0x020c4068 0xffffffff
+DATA 4 0x020c406c 0xffffffff
+DATA 4 0x020c4070 0xffffffff
+DATA 4 0x020c4074 0xffffffff
+DATA 4 0x020c4078 0xffffffff
+DATA 4 0x020c407c 0xffffffff
+DATA 4 0x020c4080 0xffffffff
+DATA 4 0x020c4084 0xffffffff
+
+/* ddr io type */
+DATA 4 0x020e04b4 0x000C0000 /* IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE */
+DATA 4 0x020e04ac 0x00000000 /* IOMUXC_SW_PAD_CTL_GRP_DDRPKE */
+
+/* clock */
+DATA 4 0x020e027c 0x00000030 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P */
+
+/* control and address */
+DATA 4 0x020E0250 0x00000030 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS */
+DATA 4 0x020E024C 0x00000030 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS */
+DATA 4 0x020E0490 0x00000030 /* IOMUXC_SW_PAD_CTL_GRP_ADDDS */
+DATA 4 0x020E0288 0x00000030 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET */
+DATA 4 0x020E0270 0x00000000 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2 - DSE can be
+ configured using Group Control Register:
+ IOMUXC_SW_PAD_CTL_GRP_CTLDS */
+DATA 4 0x020E0260 0x00000030 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0 */
+DATA 4 0x020E0264 0x00000030 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1 */
+DATA 4 0x020E04A0 0x00000030 /* IOMUXC_SW_PAD_CTL_GRP_CTLDS */
+
+/* data strobes */
+DATA 4 0x020e0494 0x00020000 /* IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL */
+DATA 4 0x020e0280 0x00000030 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P */
+DATA 4 0x020e0284 0x00000030 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P */
+
+/* data */
+DATA 4 0x020E04B0 0x00020000 /* IOMUXC_SW_PAD_CTL_GRP_DDRMODE */
+DATA 4 0x020E0498 0x00000030 /* IOMUXC_SW_PAD_CTL_GRP_B0DS */
+DATA 4 0x020E04A4 0x00000030 /* IOMUXC_SW_PAD_CTL_GRP_B1DS */
+DATA 4 0x020E0244 0x00000030 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0 */
+DATA 4 0x020E0248 0x00000030 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1 */
+
+/*
+ * DDR Controller Registers
+ *
+ * Manufacturer: IM
+ * Device Part Number: IME1G16D3EEBG-15EI
+ * Clock Freq.: 400MHz
+ * Density per CS in Gb: 1
+ * Chip Selects used: 1
+ * Number of Banks: 8
+ * Row address: 13
+ * Column address: 10
+ * Data bus width 16
+ */
+DATA 4 0x021b001c 0x00008000 /* MMDC0_MDSCR, set the Configuration request bit
+ during MMDC set up */
+
+/*
+ * Calibration setup
+ */
+DATA 4 0x021b0800 0xA1390003 /* DDR_PHY_P0_MPZQHWCTRL, enable both one-time &
+ periodic HW ZQ calibration. */
+
+/*
+ * For target board, may need to run write leveling calibration to fine tune
+ * these settings.
+ */
+DATA 4 0x021b080c 0x00000000
+
+/* Read DQS Gating calibration */
+DATA 4 0x021b083c 0x4164015C /* MPDGCTRL0 PHY0 */
+
+/* Read calibration */
+DATA 4 0x021b0848 0x40404446 /* MPRDDLCTL PHY0 */
+
+/* Write calibration */
+DATA 4 0x021b0850 0x40405A52 /* MPWRDLCTL PHY0 */
+
+/*
+ * read data bit delay: (3 is the reccommended default value, although out of
+ * reset value is 0)
+ */
+DATA 4 0x021b081c 0x33333333 /* DDR_PHY_P0_MPREDQBY0DL3 */
+DATA 4 0x021b0820 0x33333333 /* DDR_PHY_P0_MPREDQBY1DL3 */
+DATA 4 0x021b082c 0xF3333333
+DATA 4 0x021b0830 0xF3333333
+
+DATA 4 0x021b08c0 0x00921012
+
+/* Clock Fine Tuning */
+DATA 4 0x021B0858 0x00000F00 /* [MMDC_MPSDCTRL] MMDC PHY CK Control Register */
+
+/* Complete calibration by forced measurement: */
+DATA 4 0x021b08b8 0x00000800 /* DDR_PHY_P0_MPMUR0, frc_msr */
+/*
+ * Calibration setup end
+ */
+
+/* MMDC init: */
+DATA 4 0x021b0004 0x0002002D /* MMDC0_MDPDC */
+DATA 4 0x021b0008 0x1B333030 /* MMDC0_MDOTC */
+DATA 4 0x021b000c 0x3F4352F3 /* MMDC0_MDCFG0 */
+DATA 4 0x021b0010 0xB66D0B63 /* MMDC0_MDCFG1 */
+DATA 4 0x021b0014 0x01FF00DB /* MMDC0_MDCFG2 */
+
+/*
+ * MDMISC: RALAT kept to the high level of 5.
+ * MDMISC: consider reducing RALAT if your 528MHz board design allow that.
+ * Lower RALAT benefits:
+ * a. better operation at low frequency, for LPDDR2 freq < 100MHz, change RALAT
+ * to 3
+ * b. Small performence improvment
+ */
+DATA 4 0x021b0018 0x00201740 /* MMDC0_MDMISC */
+
+DATA 4 0x021b001c 0x00008000 /* MMDC0_MDSCR, set the Configuration request bit
+ during MMDC set up */
+
+DATA 4 0x021b002c 0x000026D2 /* MMDC0_MDRWD */
+DATA 4 0x021b0030 0x00431023 /* MMDC0_MDOR */
+DATA 4 0x021b0040 0x00000047 /* Chan0 CS0_END */
+DATA 4 0x021b0000 0x82180000 /* MMDC0_MDCTL */
+
+/* Mode register writes */
+DATA 4 0x021b001c 0x02008032 /* MMDC0_MDSCR, MR2 write, CS0 */
+DATA 4 0x021b001c 0x00008033 /* MMDC0_MDSCR, MR3 write, CS0 */
+DATA 4 0x021b001c 0x00048031 /* MMDC0_MDSCR, MR1 write, CS0 */
+DATA 4 0x021b001c 0x15208030 /* MMDC0_MDSCR, MR0 write, CS0 */
+DATA 4 0x021b001c 0x04008040 /* MMDC0_MDSCR, ZQ calibration command sent to
+ device on CS0 */
+
+DATA 4 0x021b0020 0x00000800 /* MMDC0_MDREF */
+DATA 4 0x021b0818 0x00000227 /* DDR_PHY_P0_MPODTCTRL */
+DATA 4 0x021b0004 0x0002556D /* MMDC0_MDPDC now SDCTL power down enabled */
+DATA 4 0x021b0404 0x00011006 /* MMDC0_MAPSR ADOPT power down enabled, MMDC will
+ enter automatically to self-refresh while the
+ number of idle cycle reached. */
+DATA 4 0x021b001c 0x00000000 /* MMDC0_MDSCR, clear this register (especially
+ the configuration bit as initialization is
+ complete) */
--- /dev/null
+/*
+ * SPL specific code for CCV xPress
+ *
+ * Copyright (C) 2015-2016 Stefan Roese <sr@denx.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <spl.h>
+#include <asm/io.h>
+#include <asm/arch/mx6-ddr.h>
+#include <asm/arch/crm_regs.h>
+
+/* Configuration for IM IME1G16D3EEBG-15EI, 64M x 16 -> 128MiB */
+
+static struct mx6ul_iomux_grp_regs mx6_grp_ioregs = {
+ .grp_addds = 0x00000030,
+ .grp_ddrmode_ctl = 0x00020000,
+ .grp_b0ds = 0x00000030,
+ .grp_ctlds = 0x00000030,
+ .grp_b1ds = 0x00000030,
+ .grp_ddrpke = 0x00000000,
+ .grp_ddrmode = 0x00020000,
+ .grp_ddr_type = 0x000c0000,
+};
+
+static struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = {
+ .dram_dqm0 = 0x00000030,
+ .dram_dqm1 = 0x00000030,
+ .dram_ras = 0x00000030,
+ .dram_cas = 0x00000030,
+ .dram_odt0 = 0x00000030,
+ .dram_odt1 = 0x00000030,
+ .dram_sdba2 = 0x00000000,
+ .dram_sdclk_0 = 0x00000008,
+ .dram_sdqs0 = 0x00000038,
+ .dram_sdqs1 = 0x00000030,
+ .dram_reset = 0x00000030,
+};
+
+static struct mx6_mmdc_calibration mx6_mmcd_calib = {
+ .p0_mpwldectrl0 = 0x00000000,
+ .p0_mpdgctrl0 = 0x4164015C,
+ .p0_mprddlctl = 0x40404446,
+ .p0_mpwrdlctl = 0x40405A52,
+};
+
+struct mx6_ddr_sysinfo ddr_sysinfo = {
+ .dsize = 0,
+ .cs_density = 20,
+ .ncs = 1,
+ .cs1_mirror = 0,
+ .rtt_wr = 2,
+ .rtt_nom = 1, /* RTT_Nom = RZQ/2 */
+ .walat = 1, /* Write additional latency */
+ .ralat = 5, /* Read additional latency */
+ .mif3_mode = 3, /* Command prediction working mode */
+ .bi_on = 1, /* Bank interleaving enabled */
+ .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
+ .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
+ .ddr_type = DDR_TYPE_DDR3,
+};
+
+static struct mx6_ddr3_cfg mem_ddr = {
+ .mem_speed = 800,
+ .density = 4,
+ .width = 16,
+ .banks = 8,
+ .rowaddr = 13,
+ .coladdr = 10,
+ .pagesz = 2,
+ .trcd = 1375,
+ .trcmin = 4875,
+ .trasmin = 3500,
+};
+
+static void ccgr_init(void)
+{
+ struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
+ writel(0xFFFFFFFF, &ccm->CCGR0);
+ writel(0xFFFFFFFF, &ccm->CCGR1);
+ writel(0xFFFFFFFF, &ccm->CCGR2);
+ writel(0xFFFFFFFF, &ccm->CCGR3);
+ writel(0xFFFFFFFF, &ccm->CCGR4);
+ writel(0xFFFFFFFF, &ccm->CCGR5);
+ writel(0xFFFFFFFF, &ccm->CCGR6);
+ writel(0xFFFFFFFF, &ccm->CCGR7);
+}
+
+static void spl_dram_init(void)
+{
+ mx6ul_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs);
+ mx6_dram_cfg(&ddr_sysinfo, &mx6_mmcd_calib, &mem_ddr);
+}
+
+void board_init_f(ulong dummy)
+{
+ /* Setup AIPS and disable watchdog */
+ arch_cpu_init();
+
+ ccgr_init();
+
+ /* Setup iomux and i2c */
+ board_early_init_f();
+
+ /* Setup GP timer */
+ timer_init();
+
+ /* UART clocks enabled and gd valid - init serial console */
+ preloader_console_init();
+
+ /* DDR initialization */
+ spl_dram_init();
+}
--- /dev/null
+/*
+ * Copyright (C) 2015-2016 Stefan Roese <sr@denx.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <asm/arch/clock.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/mx6ul_pins.h>
+#include <asm/arch/mx6-pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/gpio.h>
+#include <asm/imx-common/iomux-v3.h>
+#include <asm/imx-common/boot_mode.h>
+#include <asm/imx-common/mxc_i2c.h>
+#include <asm/io.h>
+#include <common.h>
+#include <fsl_esdhc.h>
+#include <i2c.h>
+#include <miiphy.h>
+#include <mmc.h>
+#include <netdev.h>
+#include <usb.h>
+#include <usb/ehci-fsl.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
+ PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
+ PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+
+#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
+ PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \
+ PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+
+#define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
+ PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
+ PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
+ PAD_CTL_ODE)
+
+#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
+ PAD_CTL_SPEED_HIGH | \
+ PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST)
+
+#define MDIO_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
+ PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST | PAD_CTL_ODE)
+
+#define ENET_CLK_PAD_CTRL (PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
+
+#define ENET_RX_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
+ PAD_CTL_SPEED_HIGH | PAD_CTL_SRE_FAST)
+
+#define OTGID_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
+ PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \
+ PAD_CTL_DSE_80ohm | PAD_CTL_HYS | \
+ PAD_CTL_SRE_FAST)
+
+#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
+
+static struct i2c_pads_info i2c_pad_info1 = {
+ .scl = {
+ .i2c_mode = MX6_PAD_GPIO1_IO02__I2C1_SCL | PC,
+ .gpio_mode = MX6_PAD_GPIO1_IO02__GPIO1_IO02 | PC,
+ .gp = IMX_GPIO_NR(1, 2),
+ },
+ .sda = {
+ .i2c_mode = MX6_PAD_GPIO1_IO03__I2C1_SDA | PC,
+ .gpio_mode = MX6_PAD_GPIO1_IO03__GPIO1_IO03 | PC,
+ .gp = IMX_GPIO_NR(1, 3),
+ },
+};
+
+static struct i2c_pads_info i2c_pad_info2 = {
+ .scl = {
+ .i2c_mode = MX6_PAD_GPIO1_IO00__I2C2_SCL | PC,
+ .gpio_mode = MX6_PAD_GPIO1_IO00__GPIO1_IO00 | PC,
+ .gp = IMX_GPIO_NR(1, 0),
+ },
+ .sda = {
+ .i2c_mode = MX6_PAD_GPIO1_IO01__I2C2_SDA | PC,
+ .gpio_mode = MX6_PAD_GPIO1_IO01__GPIO1_IO01 | PC,
+ .gp = IMX_GPIO_NR(1, 1),
+ },
+};
+
+static struct i2c_pads_info i2c_pad_info4 = {
+ .scl = {
+ .i2c_mode = MX6_PAD_UART2_TX_DATA__I2C4_SCL | PC,
+ .gpio_mode = MX6_PAD_UART2_TX_DATA__GPIO1_IO20 | PC,
+ .gp = IMX_GPIO_NR(1, 20),
+ },
+ .sda = {
+ .i2c_mode = MX6_PAD_UART2_RX_DATA__I2C4_SDA | PC,
+ .gpio_mode = MX6_PAD_UART2_RX_DATA__GPIO1_IO21 | PC,
+ .gp = IMX_GPIO_NR(1, 21),
+ },
+};
+
+int dram_init(void)
+{
+ gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
+
+ return 0;
+}
+
+static iomux_v3_cfg_t const uart1_pads[] = {
+ MX6_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
+ MX6_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const uart4_pads[] = {
+ MX6_PAD_UART4_TX_DATA__UART4_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
+ MX6_PAD_UART4_RX_DATA__UART4_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const uart5_pads[] = {
+ MX6_PAD_GPIO1_IO04__UART5_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
+ MX6_PAD_GPIO1_IO05__UART5_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
+ MX6_PAD_GPIO1_IO09__UART5_DCE_CTS | MUX_PAD_CTRL(UART_PAD_CTRL),
+ MX6_PAD_GPIO1_IO08__UART5_DCE_RTS | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const uart8_pads[] = {
+ MX6_PAD_ENET2_TX_DATA1__UART8_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
+ MX6_PAD_ENET2_TX_EN__UART8_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
+ MX6_PAD_ENET2_TX_CLK__UART8_DCE_CTS | MUX_PAD_CTRL(UART_PAD_CTRL),
+ MX6_PAD_ENET2_RX_ER__UART8_DCE_RTS | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+static void setup_iomux_uart(void)
+{
+ imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
+ imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads));
+ imx_iomux_v3_setup_multiple_pads(uart5_pads, ARRAY_SIZE(uart5_pads));
+ imx_iomux_v3_setup_multiple_pads(uart8_pads, ARRAY_SIZE(uart8_pads));
+}
+
+/* eMMC on USDHC2 */
+static iomux_v3_cfg_t const usdhc2_pads[] = {
+ MX6_PAD_NAND_RE_B__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_NAND_WE_B__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_NAND_DATA00__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_NAND_DATA01__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_NAND_DATA02__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_NAND_DATA03__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_NAND_DATA04__USDHC2_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_NAND_DATA05__USDHC2_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_NAND_DATA06__USDHC2_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_NAND_DATA07__USDHC2_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+
+ /*
+ * RST_B
+ */
+ MX6_PAD_NAND_ALE__USDHC2_RESET_B | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static struct fsl_esdhc_cfg usdhc_cfg = {
+ .esdhc_base = USDHC2_BASE_ADDR,
+ .max_bus_width = 8,
+};
+
+#define USDHC2_PWR_GPIO IMX_GPIO_NR(1, 9)
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+ /* eMMC is always present */
+ return 1;
+}
+
+int board_mmc_init(bd_t *bis)
+{
+ imx_iomux_v3_setup_multiple_pads(usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
+
+ usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
+
+ return fsl_esdhc_initialize(bis, &usdhc_cfg);
+}
+
+#define USB_OTHERREGS_OFFSET 0x800
+#define UCTRL_PWR_POL (1 << 9)
+
+static iomux_v3_cfg_t const usb_otg_pads[] = {
+ /* OTG1 */
+ MX6_PAD_SD1_CMD__USB_OTG1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_SD1_DATA0__ANATOP_OTG1_ID | MUX_PAD_CTRL(OTGID_PAD_CTRL),
+ /* OTG2 */
+ MX6_PAD_SD1_DATA1__USB_OTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_SD1_DATA3__ANATOP_OTG2_ID | MUX_PAD_CTRL(OTGID_PAD_CTRL),
+};
+
+static void setup_usb(void)
+{
+ imx_iomux_v3_setup_multiple_pads(usb_otg_pads,
+ ARRAY_SIZE(usb_otg_pads));
+}
+
+int board_usb_phy_mode(int port)
+{
+ if (port == 1)
+ return USB_INIT_HOST;
+ else
+ return usb_phy_mode(port);
+}
+
+int board_ehci_hcd_init(int port)
+{
+ u32 *usbnc_usb_ctrl;
+
+ if (port > 1)
+ return -EINVAL;
+
+ usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET +
+ port * 4);
+
+ /* Set Power polarity */
+ setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL);
+
+ return 0;
+}
+
+static iomux_v3_cfg_t const fec1_pads[] = {
+ MX6_PAD_GPIO1_IO06__ENET1_MDIO | MUX_PAD_CTRL(MDIO_PAD_CTRL),
+ MX6_PAD_GPIO1_IO07__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_ENET1_TX_DATA0__ENET1_TDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_ENET1_TX_DATA1__ENET1_TDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_ENET1_TX_EN__ENET1_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
+ MX6_PAD_ENET1_RX_DATA0__ENET1_RDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_ENET1_RX_DATA1__ENET1_RDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_ENET1_RX_ER__ENET1_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_ENET1_RX_EN__ENET1_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
+
+ /* ENET1 reset */
+ MX6_PAD_CSI_MCLK__GPIO4_IO17 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ /* ENET1 interrupt */
+ MX6_PAD_CSI_PIXCLK__GPIO4_IO18 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+#define ENET_PHY_RESET_GPIO IMX_GPIO_NR(4, 17)
+
+int board_eth_init(bd_t *bis)
+{
+ int ret;
+
+ imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads));
+
+ /* Reset LAN8742 PHY */
+ ret = gpio_request(ENET_PHY_RESET_GPIO, "phy-reset");
+ if (!ret)
+ gpio_direction_output(ENET_PHY_RESET_GPIO , 0);
+ mdelay(10);
+ gpio_set_value(ENET_PHY_RESET_GPIO, 1);
+ mdelay(10);
+
+ return cpu_eth_init(bis);
+}
+
+static int setup_fec(int fec_id)
+{
+ struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
+ int ret;
+
+ /*
+ * Use 50M anatop loopback REF_CLK1 for ENET1,
+ * clear gpr1[13], set gpr1[17].
+ */
+ clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK,
+ IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK);
+
+ ret = enable_fec_anatop_clock(fec_id, ENET_50MHZ);
+ if (ret)
+ return ret;
+
+ enable_enet_clk(1);
+
+ return 0;
+}
+
+int board_phy_config(struct phy_device *phydev)
+{
+ if (phydev->drv->config)
+ phydev->drv->config(phydev);
+
+ return 0;
+}
+
+int board_early_init_f(void)
+{
+ setup_iomux_uart();
+
+ return 0;
+}
+
+int board_init(void)
+{
+ /* Address of boot parameters */
+ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+ setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
+ setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
+ setup_i2c(3, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info4);
+
+ setup_fec(CONFIG_FEC_ENET_DEV);
+
+ setup_usb();
+
+ return 0;
+}
+
+static const struct boot_mode board_boot_modes[] = {
+ /* 8 bit bus width */
+ {"emmc", MAKE_CFGVAL(0x60, 0x28, 0x00, 0x00)},
+ { NULL, 0 },
+};
+
+int board_late_init(void)
+{
+ add_board_boot_modes(board_boot_modes);
+ setenv("board_name", "xpress");
+
+ return 0;
+}
+
+int checkboard(void)
+{
+ puts("Board: CCV-EVA xPress\n");
+
+ return 0;
+}
/* MMDC0_MDRWD;*/
DATA 4 0x021b002c 0x0f9f26d2
/* MMDC0_MDOR */
-DATA 4 0x021b0030 0x0000020e
+DATA 4 0x021b0030 0x009f0e10
/* MMDC0_MDCFG3LP */
DATA 4 0x021b0038 0x00190778
/* MMDC0_MDOTC */
/* MMDC1_MDRWD;*/
DATA 4 0x021b402c 0x0f9f26d2
/* MMDC1_MDOR */
-DATA 4 0x021b4030 0x0000020e
+DATA 4 0x021b4030 0x009f0e10
/* MMDC1_MDCFG3LP */
DATA 4 0x021b4038 0x00190778
/* MMDC1_MDOTC */
imx_enable_hdmi_phy();
}
-static void enable_lvds(struct display_info_t const *dev)
-{
- struct iomuxc *iomux = (struct iomuxc *)
- IOMUXC_BASE_ADDR;
- u32 reg = readl(&iomux->gpr[2]);
- reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT |
- IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT;
- writel(reg, &iomux->gpr[2]);
-}
-
struct display_info_t const displays[] = {{
.bus = -1,
.addr = 0,
.pixfmt = IPU_PIX_FMT_RGB666,
.detect = NULL,
- .enable = enable_lvds,
+ .enable = NULL,
.mode = {
.name = "Hannstar-XGA",
.refresh = 60,
.xres = 1024,
.yres = 768,
- .pixclock = 15385,
- .left_margin = 220,
- .right_margin = 40,
- .upper_margin = 21,
- .lower_margin = 7,
- .hsync_len = 60,
- .vsync_len = 10,
+ .pixclock = 15384,
+ .left_margin = 160,
+ .right_margin = 24,
+ .upper_margin = 29,
+ .lower_margin = 3,
+ .hsync_len = 136,
+ .vsync_len = 6,
.sync = FB_SYNC_EXT,
.vmode = FB_VMODE_NONINTERLACED
} }, {
.refresh = 60,
.xres = 1024,
.yres = 768,
- .pixclock = 15385,
- .left_margin = 220,
- .right_margin = 40,
- .upper_margin = 21,
- .lower_margin = 7,
- .hsync_len = 60,
- .vsync_len = 10,
+ .pixclock = 15384,
+ .left_margin = 160,
+ .right_margin = 24,
+ .upper_margin = 29,
+ .lower_margin = 3,
+ .hsync_len = 136,
+ .vsync_len = 6,
.sync = FB_SYNC_EXT,
.vmode = FB_VMODE_NONINTERLACED
} }, {
DATA 4 0x021b001c 0x00008000
DATA 4 0x021b085c 0x1b4700c7
DATA 4 0x021b0800 0xa1390003
-DATA 4 0x021b0890 0x00300000
+DATA 4 0x021b0890 0x00400000
DATA 4 0x021b08b8 0x00000800
DATA 4 0x021b081c 0x33333333
DATA 4 0x021b0820 0x33333333
DATA 4 0x021b0014 0x00000093
DATA 4 0x021b0018 0x00001688
DATA 4 0x021b002c 0x0f9f26d2
-DATA 4 0x021b0030 0x0000020e
+DATA 4 0x021b0030 0x009f0e10
DATA 4 0x021b0038 0x00190778
DATA 4 0x021b0008 0x00000000
DATA 4 0x021b0040 0x0000004f
--- /dev/null
+if TARGET_GE_B450V3 || TARGET_GE_B650V3 || TARGET_GE_B850V3
+
+config IMX_CONFIG
+ default "board/ge/bx50v3/bx50v3.cfg"
+
+config SYS_BOARD
+ default "bx50v3"
+
+config SYS_VENDOR
+ default "ge"
+
+config SYS_SOC
+ default "mx6"
+
+config SYS_CONFIG_NAME
+ default "ge_bx50v3"
+
+endif
--- /dev/null
+GE_BX50V3 BOARD
+M: Martin Donnelly <martin.donnelly@ge.com>
+S: Maintained
+F: board/ge/bx50v3/
+F: include/configs/ge_bx50v3.h
+F: configs/ge_b450v3_defconfig
+F: configs/ge_b650v3_defconfig
+F: configs/ge_b850v3_defconfig
--- /dev/null
+#
+# Copyright 2015 Timesys Corporation
+# Copyright 2015 General Electric Company
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := bx50v3.o
--- /dev/null
+/*
+ * Copyright 2015 Timesys Corporation
+ * Copyright 2015 General Electric Company
+ * Copyright 2012 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <asm/arch/clock.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/mx6-pins.h>
+#include <asm/errno.h>
+#include <asm/gpio.h>
+#include <asm/imx-common/mxc_i2c.h>
+#include <asm/imx-common/iomux-v3.h>
+#include <asm/imx-common/boot_mode.h>
+#include <asm/imx-common/video.h>
+#include <mmc.h>
+#include <fsl_esdhc.h>
+#include <miiphy.h>
+#include <netdev.h>
+#include <asm/arch/mxc_hdmi.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/io.h>
+#include <asm/arch/sys_proto.h>
+#include <i2c.h>
+DECLARE_GLOBAL_DATA_PTR;
+
+#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
+ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
+ PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+
+#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
+ PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
+ PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+
+#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
+ PAD_CTL_SPEED_HIGH | PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST)
+
+#define ENET_CLK_PAD_CTRL (PAD_CTL_SPEED_MED | \
+ PAD_CTL_DSE_120ohm | PAD_CTL_SRE_FAST)
+
+#define ENET_RX_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
+ PAD_CTL_SPEED_HIGH | PAD_CTL_SRE_FAST)
+
+#define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
+ PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
+
+#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
+ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
+ PAD_CTL_ODE | PAD_CTL_SRE_FAST)
+
+#define I2C_PAD MUX_PAD_CTRL(I2C_PAD_CTRL)
+
+int dram_init(void)
+{
+ gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
+
+ return 0;
+}
+
+static iomux_v3_cfg_t const uart3_pads[] = {
+ MX6_PAD_EIM_D31__UART3_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
+ MX6_PAD_EIM_D23__UART3_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
+ MX6_PAD_EIM_D24__UART3_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+ MX6_PAD_EIM_D25__UART3_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const uart4_pads[] = {
+ MX6_PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+ MX6_PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const enet_pads[] = {
+ MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
+ MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
+ MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
+ MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
+ MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
+ MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
+ MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
+ /* AR8033 PHY Reset */
+ MX6_PAD_ENET_TX_EN__GPIO1_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static void setup_iomux_enet(void)
+{
+ imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
+
+ /* Reset AR8033 PHY */
+ gpio_direction_output(IMX_GPIO_NR(1, 28), 0);
+ udelay(500);
+ gpio_set_value(IMX_GPIO_NR(1, 28), 1);
+}
+
+static iomux_v3_cfg_t const usdhc2_pads[] = {
+ MX6_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_GPIO_4__GPIO1_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const usdhc3_pads[] = {
+ MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_RST__SD3_RESET | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const usdhc4_pads[] = {
+ MX6_PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_NANDF_CS0__GPIO6_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_NANDF_CS1__GPIO6_IO14 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const ecspi1_pads[] = {
+ MX6_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
+ MX6_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
+ MX6_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
+ MX6_PAD_EIM_EB2__GPIO2_IO30 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static struct i2c_pads_info i2c_pad_info1 = {
+ .scl = {
+ .i2c_mode = MX6_PAD_CSI0_DAT9__I2C1_SCL | I2C_PAD,
+ .gpio_mode = MX6_PAD_CSI0_DAT9__GPIO5_IO27 | I2C_PAD,
+ .gp = IMX_GPIO_NR(5, 27)
+ },
+ .sda = {
+ .i2c_mode = MX6_PAD_CSI0_DAT8__I2C1_SDA | I2C_PAD,
+ .gpio_mode = MX6_PAD_CSI0_DAT8__GPIO5_IO26 | I2C_PAD,
+ .gp = IMX_GPIO_NR(5, 26)
+ }
+};
+
+static struct i2c_pads_info i2c_pad_info2 = {
+ .scl = {
+ .i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | I2C_PAD,
+ .gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12 | I2C_PAD,
+ .gp = IMX_GPIO_NR(4, 12)
+ },
+ .sda = {
+ .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | I2C_PAD,
+ .gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | I2C_PAD,
+ .gp = IMX_GPIO_NR(4, 13)
+ }
+};
+
+static struct i2c_pads_info i2c_pad_info3 = {
+ .scl = {
+ .i2c_mode = MX6_PAD_GPIO_3__I2C3_SCL | I2C_PAD,
+ .gpio_mode = MX6_PAD_GPIO_3__GPIO1_IO03 | I2C_PAD,
+ .gp = IMX_GPIO_NR(1, 3)
+ },
+ .sda = {
+ .i2c_mode = MX6_PAD_GPIO_6__I2C3_SDA | I2C_PAD,
+ .gpio_mode = MX6_PAD_GPIO_6__GPIO1_IO06 | I2C_PAD,
+ .gp = IMX_GPIO_NR(1, 6)
+ }
+};
+
+#ifdef CONFIG_MXC_SPI
+int board_spi_cs_gpio(unsigned bus, unsigned cs)
+{
+ return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(2, 30)) : -1;
+}
+
+static void setup_spi(void)
+{
+ imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads));
+}
+#endif
+
+static iomux_v3_cfg_t const pcie_pads[] = {
+ MX6_PAD_GPIO_5__GPIO1_IO05 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_GPIO_17__GPIO7_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static void setup_pcie(void)
+{
+ imx_iomux_v3_setup_multiple_pads(pcie_pads, ARRAY_SIZE(pcie_pads));
+}
+
+static void setup_iomux_uart(void)
+{
+ imx_iomux_v3_setup_multiple_pads(uart3_pads, ARRAY_SIZE(uart3_pads));
+ imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads));
+}
+
+#ifdef CONFIG_FSL_ESDHC
+struct fsl_esdhc_cfg usdhc_cfg[3] = {
+ {USDHC2_BASE_ADDR},
+ {USDHC3_BASE_ADDR},
+ {USDHC4_BASE_ADDR},
+};
+
+#define USDHC2_CD_GPIO IMX_GPIO_NR(1, 4)
+#define USDHC4_CD_GPIO IMX_GPIO_NR(6, 11)
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+ struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+ int ret = 0;
+
+ switch (cfg->esdhc_base) {
+ case USDHC2_BASE_ADDR:
+ ret = !gpio_get_value(USDHC2_CD_GPIO);
+ break;
+ case USDHC3_BASE_ADDR:
+ ret = 1; /* eMMC is always present */
+ break;
+ case USDHC4_BASE_ADDR:
+ ret = !gpio_get_value(USDHC4_CD_GPIO);
+ break;
+ }
+
+ return ret;
+}
+
+int board_mmc_init(bd_t *bis)
+{
+ int ret;
+ int i;
+
+ for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
+ switch (i) {
+ case 0:
+ imx_iomux_v3_setup_multiple_pads(
+ usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
+ gpio_direction_input(USDHC2_CD_GPIO);
+ usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
+ break;
+ case 1:
+ imx_iomux_v3_setup_multiple_pads(
+ usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
+ usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+ break;
+ case 2:
+ imx_iomux_v3_setup_multiple_pads(
+ usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
+ gpio_direction_input(USDHC4_CD_GPIO);
+ usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
+ break;
+ default:
+ printf("Warning: you configured more USDHC controllers\n"
+ "(%d) then supported by the board (%d)\n",
+ i + 1, CONFIG_SYS_FSL_USDHC_NUM);
+ return -EINVAL;
+ }
+
+ ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
+#endif
+
+static int mx6_rgmii_rework(struct phy_device *phydev)
+{
+ /* Configure AR8033 to ouput a 125MHz clk from CLK_25M */
+ /* set device address 0x7 */
+ phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
+ /* offset 0x8016: CLK_25M Clock Select */
+ phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
+ /* enable register write, no post increment, address 0x7 */
+ phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
+ /* set to 125 MHz from local PLL source */
+ phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x18);
+
+ /* rgmii tx clock delay enable */
+ /* set debug port address: SerDes Test and System Mode Control */
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
+ /* enable rgmii tx clock delay */
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
+
+ return 0;
+}
+
+int board_phy_config(struct phy_device *phydev)
+{
+ mx6_rgmii_rework(phydev);
+
+ if (phydev->drv->config)
+ phydev->drv->config(phydev);
+
+ return 0;
+}
+
+#if defined(CONFIG_VIDEO_IPUV3)
+static iomux_v3_cfg_t const backlight_pads[] = {
+ /* Power for LVDS Display */
+ MX6_PAD_EIM_D22__GPIO3_IO22 | MUX_PAD_CTRL(NO_PAD_CTRL),
+#define LVDS_POWER_GP IMX_GPIO_NR(3, 22)
+ /* Backlight enable for LVDS display */
+ MX6_PAD_GPIO_0__GPIO1_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL),
+#define LVDS_BACKLIGHT_GP IMX_GPIO_NR(1, 0)
+};
+
+static void do_enable_hdmi(struct display_info_t const *dev)
+{
+ imx_enable_hdmi_phy();
+}
+
+int board_cfb_skip(void)
+{
+ gpio_direction_output(LVDS_POWER_GP, 1);
+
+ return 0;
+}
+
+static int detect_baseboard(struct display_info_t const *dev)
+{
+ if (IS_ENABLED(CONFIG_TARGET_GE_B450V3) ||
+ IS_ENABLED(CONFIG_TARGET_GE_B650V3))
+ return 1;
+
+ return 0;
+}
+
+struct display_info_t const displays[] = {{
+ .bus = -1,
+ .addr = -1,
+ .pixfmt = IPU_PIX_FMT_RGB24,
+ .detect = detect_baseboard,
+ .enable = NULL,
+ .mode = {
+ .name = "G121X1-L03",
+ .refresh = 60,
+ .xres = 1024,
+ .yres = 768,
+ .pixclock = 15385,
+ .left_margin = 20,
+ .right_margin = 300,
+ .upper_margin = 30,
+ .lower_margin = 8,
+ .hsync_len = 1,
+ .vsync_len = 1,
+ .sync = FB_SYNC_EXT,
+ .vmode = FB_VMODE_NONINTERLACED
+} }, {
+ .bus = -1,
+ .addr = 3,
+ .pixfmt = IPU_PIX_FMT_RGB24,
+ .detect = detect_hdmi,
+ .enable = do_enable_hdmi,
+ .mode = {
+ .name = "HDMI",
+ .refresh = 60,
+ .xres = 1024,
+ .yres = 768,
+ .pixclock = 15385,
+ .left_margin = 220,
+ .right_margin = 40,
+ .upper_margin = 21,
+ .lower_margin = 7,
+ .hsync_len = 60,
+ .vsync_len = 10,
+ .sync = FB_SYNC_EXT,
+ .vmode = FB_VMODE_NONINTERLACED
+} } };
+size_t display_count = ARRAY_SIZE(displays);
+
+static void setup_display(void)
+{
+ struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+ struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
+ int reg;
+
+ enable_ipu_clock();
+ imx_setup_hdmi();
+
+ reg = readl(&mxc_ccm->CCGR3);
+ reg |= MXC_CCM_CCGR3_LDB_DI0_MASK;
+ writel(reg, &mxc_ccm->CCGR3);
+
+ reg = readl(&mxc_ccm->cs2cdr);
+ reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK |
+ MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
+ reg |= (3 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET) |
+ (3 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
+ writel(reg, &mxc_ccm->cs2cdr);
+
+ reg = readl(&mxc_ccm->cscmr2);
+ reg |= (MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV);
+ writel(reg, &mxc_ccm->cscmr2);
+
+ reg = readl(&mxc_ccm->chsccdr);
+ reg |= (CHSCCDR_CLK_SEL_LDB_DI0
+ << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
+ writel(reg, &mxc_ccm->chsccdr);
+
+ reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
+ | IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH
+ | IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
+ | IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
+ | IOMUXC_GPR2_DATA_WIDTH_CH1_24BIT
+ | IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
+ | IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT
+ | IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI0
+ | IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
+ writel(reg, &iomux->gpr[2]);
+
+ reg = readl(&iomux->gpr[3]);
+ reg = (reg & ~(IOMUXC_GPR3_LVDS0_MUX_CTL_MASK |
+ IOMUXC_GPR3_LVDS1_MUX_CTL_MASK |
+ IOMUXC_GPR3_HDMI_MUX_CTL_MASK))
+ | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
+ << IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET)
+ | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
+ << IOMUXC_GPR3_LVDS1_MUX_CTL_OFFSET);
+ writel(reg, &iomux->gpr[3]);
+
+ /* backlights off until needed */
+ imx_iomux_v3_setup_multiple_pads(backlight_pads,
+ ARRAY_SIZE(backlight_pads));
+ gpio_direction_input(LVDS_POWER_GP);
+ gpio_direction_input(LVDS_BACKLIGHT_GP);
+}
+#endif /* CONFIG_VIDEO_IPUV3 */
+
+/*
+ * Do not overwrite the console
+ * Use always serial for U-Boot console
+ */
+int overwrite_console(void)
+{
+ return 1;
+}
+
+int board_eth_init(bd_t *bis)
+{
+ setup_iomux_enet();
+ setup_pcie();
+
+ return cpu_eth_init(bis);
+}
+
+static iomux_v3_cfg_t const misc_pads[] = {
+ MX6_PAD_KEY_ROW2__GPIO4_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+#define SUS_S3_OUT IMX_GPIO_NR(4, 11)
+#define WIFI_EN IMX_GPIO_NR(6, 14)
+
+int board_early_init_f(void)
+{
+ imx_iomux_v3_setup_multiple_pads(misc_pads,
+ ARRAY_SIZE(misc_pads));
+
+ setup_iomux_uart();
+
+
+ return 0;
+}
+
+int board_init(void)
+{
+ gpio_direction_output(SUS_S3_OUT, 1);
+ gpio_direction_output(WIFI_EN, 1);
+#if defined(CONFIG_VIDEO_IPUV3)
+ setup_display();
+#endif
+ /* address of boot parameters */
+ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+#ifdef CONFIG_MXC_SPI
+ setup_spi();
+#endif
+ setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
+ setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
+ setup_i2c(3, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info3);
+
+ return 0;
+}
+
+#ifdef CONFIG_CMD_BMODE
+static const struct boot_mode board_boot_modes[] = {
+ /* 4 bit bus width */
+ {"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
+ {"sd3", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
+ {NULL, 0},
+};
+#endif
+
+int board_late_init(void)
+{
+#ifdef CONFIG_CMD_BMODE
+ add_board_boot_modes(board_boot_modes);
+#endif
+ /* We need at least 200ms between power on and backlight on
+ * as per specifications from CHI MEI */
+ mdelay(250);
+
+ /* Backlight Power */
+ gpio_direction_output(LVDS_BACKLIGHT_GP, 1);
+
+ return 0;
+}
+
+int checkboard(void)
+{
+ printf("BOARD: %s\n", CONFIG_BOARD_NAME);
+ return 0;
+}
--- /dev/null
+/*
+ *
+ * Copyright 2015 Timesys Corporation.
+ * Copyright 2015 General Electric Company
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * Refer doc/README.imximage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+
+IMAGE_VERSION 2
+BOOT_FROM sd
+
+#define __ASSEMBLY__
+#include <config.h>
+#include "asm/arch/mx6-ddr.h"
+#include "asm/arch/iomux.h"
+#include "asm/arch/crm_regs.h"
+
+/* DDR IO */
+DATA 4, MX6_IOM_GRP_DDR_TYPE, 0x000c0000
+DATA 4, MX6_IOM_GRP_DDRPKE, 0x00000000
+DATA 4, MX6_IOM_DRAM_SDCLK_0, 0x00000030
+DATA 4, MX6_IOM_DRAM_SDCLK_1, 0x00000030
+DATA 4, MX6_IOM_DRAM_CAS, 0x00000030
+DATA 4, MX6_IOM_DRAM_RAS, 0x00000030
+DATA 4, MX6_IOM_GRP_ADDDS, 0x00000030
+DATA 4, MX6_IOM_DRAM_RESET, 0x00000030
+DATA 4, MX6_IOM_DRAM_SDBA2, 0x00000000
+DATA 4, MX6_IOM_DRAM_SDODT0, 0x00000030
+DATA 4, MX6_IOM_DRAM_SDODT1, 0x00000030
+DATA 4, MX6_IOM_GRP_CTLDS, 0x00000030
+DATA 4, MX6_IOM_DDRMODE_CTL, 0x00020000
+DATA 4, MX6_IOM_DRAM_SDQS0, 0x00000030
+DATA 4, MX6_IOM_DRAM_SDQS1, 0x00000030
+DATA 4, MX6_IOM_DRAM_SDQS2, 0x00000030
+DATA 4, MX6_IOM_DRAM_SDQS3, 0x00000030
+DATA 4, MX6_IOM_DRAM_SDQS4, 0x00000030
+DATA 4, MX6_IOM_DRAM_SDQS5, 0x00000030
+DATA 4, MX6_IOM_DRAM_SDQS6, 0x00000030
+DATA 4, MX6_IOM_DRAM_SDQS7, 0x00000030
+DATA 4, MX6_IOM_GRP_DDRMODE, 0x00020000
+DATA 4, MX6_IOM_GRP_B0DS, 0x00000030
+DATA 4, MX6_IOM_GRP_B1DS, 0x00000030
+DATA 4, MX6_IOM_GRP_B2DS, 0x00000030
+DATA 4, MX6_IOM_GRP_B3DS, 0x00000030
+DATA 4, MX6_IOM_GRP_B4DS, 0x00000030
+DATA 4, MX6_IOM_GRP_B5DS, 0x00000030
+DATA 4, MX6_IOM_GRP_B6DS, 0x00000030
+DATA 4, MX6_IOM_GRP_B7DS, 0x00000030
+DATA 4, MX6_IOM_DRAM_DQM0, 0x00000030
+DATA 4, MX6_IOM_DRAM_DQM1, 0x00000030
+DATA 4, MX6_IOM_DRAM_DQM2, 0x00000030
+DATA 4, MX6_IOM_DRAM_DQM3, 0x00000030
+DATA 4, MX6_IOM_DRAM_DQM4, 0x00000030
+DATA 4, MX6_IOM_DRAM_DQM5, 0x00000030
+DATA 4, MX6_IOM_DRAM_DQM6, 0x00000030
+DATA 4, MX6_IOM_DRAM_DQM7, 0x00000030
+
+/* Calibrations */
+/* ZQ */
+DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xa1390003
+/* write leveling */
+DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x001F001F
+DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x001F001F
+DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x001F001F
+DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x001F001F
+/* Read DQS Gating calibration */
+DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x45380544
+DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x05280530
+DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x4530053C
+DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x0530050C
+/* Read calibration */
+DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x36303032
+DATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x38363042
+/* Write calibration */
+DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x3A3A423E
+DATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x4A38483E
+/* read data bit delay */
+DATA 4, MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333
+DATA 4, MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333
+DATA 4, MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333
+DATA 4, MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333
+DATA 4, MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333
+DATA 4, MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333
+DATA 4, MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333
+DATA 4, MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333
+
+/* Complete calibration by forced measurment */
+DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800
+DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000800
+
+/* MMDC init */
+DATA 4, MX6_MMDC_P0_MDPDC, 0x00020036
+DATA 4, MX6_MMDC_P0_MDOTC, 0x09444040
+DATA 4, MX6_MMDC_P0_MDCFG0, 0x8A8F79A4
+DATA 4, MX6_MMDC_P0_MDCFG1, 0xDB538E64
+DATA 4, MX6_MMDC_P0_MDCFG2, 0x01ff00db
+DATA 4, MX6_MMDC_P0_MDMISC, 0x00001740
+DATA 4, MX6_MMDC_P0_MDSCR, 0x00008000
+DATA 4, MX6_MMDC_P0_MDRWD, 0x000026d2
+DATA 4, MX6_MMDC_P0_MDOR, 0x008F1023
+DATA 4, MX6_MMDC_P0_MDASP, 0x00000047
+DATA 4, MX6_MMDC_P0_MDCTL, 0x841a0000
+
+/* Initialize Micron MT41J128M */
+DATA 4, MX6_MMDC_P0_MDSCR, 0x04088032
+DATA 4, MX6_MMDC_P0_MDSCR, 0x0408803a
+DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033
+DATA 4, MX6_MMDC_P0_MDSCR, 0x0000803b
+DATA 4, MX6_MMDC_P0_MDSCR, 0x00408031
+DATA 4, MX6_MMDC_P0_MDSCR, 0x00408039
+DATA 4, MX6_MMDC_P0_MDSCR, 0x09408030
+DATA 4, MX6_MMDC_P0_MDSCR, 0x09408038
+DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040
+DATA 4, MX6_MMDC_P0_MDSCR, 0x04008048
+DATA 4, MX6_MMDC_P0_MDREF, 0x00005800
+DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00011117
+DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00011117
+DATA 4, MX6_MMDC_P0_MDPDC, 0x00025576
+DATA 4, MX6_MMDC_P0_MAPSR, 0x00011006
+DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000
+
+/* set the default clock gate to save power */
+DATA 4, CCM_CCGR0, 0x00C03F3F
+DATA 4, CCM_CCGR1, 0x0030FC03
+DATA 4, CCM_CCGR2, 0x0FFFC000
+DATA 4, CCM_CCGR3, 0x3FF00000
+DATA 4, CCM_CCGR4, 0x00FFF300
+DATA 4, CCM_CCGR5, 0x0F0000C3
+DATA 4, CCM_CCGR6, 0x000003FF
+
+/* enable AXI cache for VDOA/VPU/IPU */
+DATA 4, MX6_IOMUXC_GPR4, 0xF00000CF
+/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
+DATA 4, MX6_IOMUXC_GPR6, 0x007F007F
+DATA 4, MX6_IOMUXC_GPR7, 0x007F007F
+
+/*
+ * Setup CCM_CCOSR register as follows:
+ *
+ * cko1_en 1 --> CKO1 enabled
+ * cko1_div 111 --> divide by 8
+ * cko1_sel 1011 --> ahb_clk_root
+ *
+ * This sets CKO1 at ahb_clk_root/8 132/8 16.5 MHz
+ */
+DATA 4, CCM_CCOSR, 0x000000fb
--- /dev/null
+if TARGET_WARP7
+
+config SYS_BOARD
+ default "warp7"
+
+config SYS_CONFIG_NAME
+ default "warp7"
+
+endif
--- /dev/null
+WARP7 BOARD
+M: Fabio Estevam <fabio.estevam@nxp.com>
+S: Maintained
+F: board/warp7/
+F: include/configs/warp7.h
+F: configs/warp7_defconfig
--- /dev/null
+# (C) Copyright 2016 NXP Semiconductors
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := warp7.o
--- /dev/null
+/*
+ * Copyright (C) 2016 NXP Semiconductors
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ *
+ * Refer docs/README.imxmage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+
+#define __ASSEMBLY__
+#include <config.h>
+
+IMAGE_VERSION 2
+BOOT_FROM sd
+
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type Address Value
+ *
+ * where:
+ * Addr-type register length (1,2 or 4 bytes)
+ * Address absolute address of the register
+ * value value to be stored in the register
+ */
+
+DATA 4 0x30340004 0x4F400005
+
+DATA 4 0x30391000 0x00000002
+DATA 4 0x307a0000 0x03040008
+DATA 4 0x307a0064 0x00200038
+DATA 4 0x307a0490 0x00000001
+DATA 4 0x307a00d0 0x00350001
+DATA 4 0x307a00dc 0x00c3000a
+DATA 4 0x307a00e0 0x00010000
+DATA 4 0x307a00e4 0x00110006
+DATA 4 0x307a00f4 0x0000033f
+DATA 4 0x307a0100 0x0a0e110b
+DATA 4 0x307a0104 0x00020211
+DATA 4 0x307a0108 0x03060708
+DATA 4 0x307a010c 0x00a0500c
+DATA 4 0x307a0110 0x05020307
+DATA 4 0x307a0114 0x02020404
+DATA 4 0x307a0118 0x02020003
+DATA 4 0x307a011c 0x00000202
+DATA 4 0x307a0120 0x00000202
+
+DATA 4 0x307a0180 0x00600018
+DATA 4 0x307a0184 0x00e00100
+DATA 4 0x307a0190 0x02098205
+DATA 4 0x307a0194 0x00060303
+DATA 4 0x307a01a0 0x80400003
+DATA 4 0x307a01a4 0x00100020
+DATA 4 0x307a01a8 0x80100004
+
+DATA 4 0x307a0200 0x00000015
+DATA 4 0x307a0204 0x00161616
+DATA 4 0x307a0210 0x00000f0f
+DATA 4 0x307a0214 0x04040404
+DATA 4 0x307a0218 0x0f0f0404
+
+DATA 4 0x307a0240 0x06000600
+DATA 4 0x307a0244 0x00000000
+DATA 4 0x30391000 0x00000000
+DATA 4 0x30790000 0x17421e40
+DATA 4 0x30790004 0x10210100
+DATA 4 0x30790008 0x00010000
+DATA 4 0x30790010 0x0007080c
+DATA 4 0x307900b0 0x1010007e
+
+DATA 4 0x3079001C 0x01010000
+DATA 4 0x3079009c 0x00000d6e
+
+DATA 4 0x30790030 0x06060606
+DATA 4 0x30790020 0x0a0a0a0a
+DATA 4 0x30790050 0x01000008
+DATA 4 0x30790050 0x00000008
+DATA 4 0x30790018 0x0000000f
+DATA 4 0x307900c0 0x0e487304
+DATA 4 0x307900c0 0x0e4c7304
+DATA 4 0x307900c0 0x0e4c7306
+DATA 4 0x307900c0 0x0e4c7304
+
+CHECK_BITS_SET 4 0x307900c4 0x1
+
+DATA 4 0x307900c0 0x0e487304
+
+DATA 4 0x30384130 0x00000000
+DATA 4 0x30340020 0x00000178
+DATA 4 0x30384130 0x00000002
+
+CHECK_BITS_SET 4 0x307a0004 0x1
--- /dev/null
+/*
+ * Copyright (C) 2016 NXP Semiconductors
+ * Author: Fabio Estevam <fabio.estevam@nxp.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <asm/arch/clock.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/mx7-pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/gpio.h>
+#include <asm/imx-common/iomux-v3.h>
+#include <asm/io.h>
+#include <common.h>
+#include <fsl_esdhc.h>
+#include <mmc.h>
+#include <asm/arch/crm_regs.h>
+#include <usb.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define UART_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_PUS_PU100KOHM | \
+ PAD_CTL_HYS)
+#define USDHC_PAD_CTRL (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \
+ PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU47KOHM)
+
+int dram_init(void)
+{
+ gd->ram_size = PHYS_SDRAM_SIZE;
+
+ return 0;
+}
+
+static iomux_v3_cfg_t const uart1_pads[] = {
+ MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
+ MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const usdhc3_pads[] = {
+ MX7D_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX7D_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX7D_PAD_SD3_DATA0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX7D_PAD_SD3_DATA1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX7D_PAD_SD3_DATA2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX7D_PAD_SD3_DATA3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX7D_PAD_SD3_DATA4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX7D_PAD_SD3_DATA5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX7D_PAD_SD3_DATA6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX7D_PAD_SD3_DATA7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX7D_PAD_SD3_RESET_B__SD3_RESET_B | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+};
+
+static void setup_iomux_uart(void)
+{
+ imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
+};
+
+static struct fsl_esdhc_cfg usdhc_cfg[1] = {
+ {USDHC3_BASE_ADDR},
+};
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+ /* Assume uSDHC3 emmc is always present */
+ return 1;
+}
+
+int board_mmc_init(bd_t *bis)
+{
+ imx_iomux_v3_setup_multiple_pads(usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
+ usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+
+ return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
+}
+
+int board_early_init_f(void)
+{
+ setup_iomux_uart();
+
+ return 0;
+}
+
+int board_init(void)
+{
+ /* address of boot parameters */
+ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+ return 0;
+}
+
+int checkboard(void)
+{
+ puts("Board: WARP7\n");
+
+ return 0;
+}
+
+int board_usb_phy_mode(int port)
+{
+ return USB_INIT_DEVICE;
+}
--- /dev/null
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_TARGET_GE_B450V3=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_GPIO=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_TARGET_GE_B650V3=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_GPIO=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_TARGET_GE_B850V3=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_GPIO=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
CONFIG_ARM=y
CONFIG_TARGET_MX28EVK=y
CONFIG_SPL=y
+CONFIG_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="ENV_IS_IN_MMC"
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
CONFIG_TARGET_MX6SXSABREAUTO=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sxsabreauto/imximage.cfg,MX6SX"
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sxsabreauto/imximage.cfg"
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
CONFIG_TARGET_MX6SXSABRESD=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sxsabresd/imximage.cfg,MX6SX"
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sxsabresd/imximage.cfg"
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
CONFIG_ARCH_MX6=y
CONFIG_TARGET_MX6SXSABRESD=y
CONFIG_SPL=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6SX"
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg"
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
CONFIG_TARGET_MX7DSABRESD=y
CONFIG_IMX_RDC=y
CONFIG_IMX_BOOTAUX=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx7dsabresd/imximage.cfg,MX7D"
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx7dsabresd/imximage.cfg"
# CONFIG_CMD_BOOTD is not set
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_IMLS is not set
--- /dev/null
+CONFIG_ARM=y
+CONFIG_ARCH_MX7=y
+CONFIG_TARGET_WARP7=y
+CONFIG_IMX_RDC=y
+CONFIG_IMX_BOOTAUX=y
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/warp7/imximage.cfg"
+# CONFIG_CMD_BOOTD is not set
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_XIMG is not set
+CONFIG_CMD_GPIO=y
+# CONFIG_CMD_SETEXPR is not set
--- /dev/null
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_TARGET_XPRESS=y
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/ccv/xpress/imximage.cfg"
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_TARGET_XPRESS=y
+CONFIG_SPL=y
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg"
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
--- /dev/null
+/*
+ * Copyright (C) 2015 Timesys Corporation
+ * Copyright (C) 2015 General Electric Company
+ * Copyright (C) 2014 Advantech
+ * Copyright (C) 2012 Freescale Semiconductor, Inc.
+ *
+ * Configuration settings for the GE MX6Q Bx50v3 boards.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __GE_BX50V3_CONFIG_H
+#define __GE_BX50V3_CONFIG_H
+
+#include <asm/arch/imx-regs.h>
+#include <asm/imx-common/gpio.h>
+
+#if defined(CONFIG_TARGET_GE_B450V3)
+#define CONFIG_BOARD_NAME "General Electric B450v3"
+#define CONFIG_DEFAULT_FDT_FILE "/boot/imx6q-b450v3.dtb"
+#elif defined(CONFIG_TARGET_GE_B650V3)
+#define CONFIG_BOARD_NAME "General Electric B650v3"
+#define CONFIG_DEFAULT_FDT_FILE "/boot/imx6q-b650v3.dtb"
+#elif defined(CONFIG_TARGET_GE_B850V3)
+#define CONFIG_BOARD_NAME "General Electric B850v3"
+#define CONFIG_DEFAULT_FDT_FILE "/boot/imx6q-b850v3.dtb"
+#else
+#define CONFIG_BOARD_NAME "General Electric BA16 Generic"
+#define CONFIG_DEFAULT_FDT_FILE "/boot/imx6q-ba16.dtb"
+#endif
+
+#define CONFIG_MXC_UART_BASE UART3_BASE
+#define CONFIG_CONSOLE_DEV "ttymxc2"
+
+#define PHYS_SDRAM_SIZE (2u * 1024 * 1024 * 1024)
+
+#define CONFIG_SUPPORT_EMMC_BOOT
+
+#define CONFIG_BOOTDELAY 1
+
+#include "mx6_common.h"
+#include <linux/sizes.h>
+
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+#define CONFIG_REVISION_TAG
+#define CONFIG_SYS_MALLOC_LEN (10 * SZ_1M)
+
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_BOARD_LATE_INIT
+
+#define CONFIG_MXC_GPIO
+#define CONFIG_MXC_UART
+
+#define CONFIG_CMD_FUSE
+#define CONFIG_MXC_OCOTP
+
+/* SATA Configs */
+#define CONFIG_CMD_SATA
+#define CONFIG_DWC_AHSATA
+#define CONFIG_SYS_SATA_MAX_DEVICE 1
+#define CONFIG_DWC_AHSATA_PORT_ID 0
+#define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR
+#define CONFIG_LBA48
+#define CONFIG_LIBATA
+
+/* MMC Configs */
+#define CONFIG_FSL_ESDHC
+#define CONFIG_FSL_USDHC
+#define CONFIG_SYS_FSL_ESDHC_ADDR 0
+#define CONFIG_MMC
+#define CONFIG_CMD_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_BOUNCE_BUFFER
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_DOS_PARTITION
+
+/* USB Configs */
+#define CONFIG_CMD_USB
+#define CONFIG_CMD_FAT
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_MX6
+#define CONFIG_USB_STORAGE
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
+#define CONFIG_MXC_USB_FLAGS 0
+#define CONFIG_USB_KEYBOARD
+#define CONFIG_SYS_USB_EVENT_POLL_VIA_CONTROL_EP
+
+#define CONFIG_CI_UDC
+#define CONFIG_USBD_HS
+#define CONFIG_USB_GADGET_DUALSPEED
+#define CONFIG_USB_GADGET
+#define CONFIG_USB_GADGET_DOWNLOAD
+#define CONFIG_CMD_USB_MASS_STORAGE
+#define CONFIG_USB_GADGET_MASS_STORAGE
+#define CONFIG_USB_FUNCTION_MASS_STORAGE
+#define CONFIG_USB_GADGET_VBUS_DRAW 2
+#define CONFIG_G_DNL_VENDOR_NUM 0x0525
+#define CONFIG_G_DNL_PRODUCT_NUM 0xa4a5
+#define CONFIG_G_DNL_MANUFACTURER "Advantech"
+
+/* Networking Configs */
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_MII
+#define CONFIG_FEC_MXC
+#define CONFIG_MII
+#define IMX_FEC_BASE ENET_BASE_ADDR
+#define CONFIG_FEC_XCV_TYPE RGMII
+#define CONFIG_ETHPRIME "FEC"
+#define CONFIG_FEC_MXC_PHYADDR 4
+#define CONFIG_PHYLIB
+#define CONFIG_PHY_ATHEROS
+
+/* Serial Flash */
+#define CONFIG_CMD_SF
+#ifdef CONFIG_CMD_SF
+#define CONFIG_MXC_SPI
+#define CONFIG_SF_DEFAULT_BUS 0
+#define CONFIG_SF_DEFAULT_CS 0
+#define CONFIG_SF_DEFAULT_SPEED 20000000
+#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
+#endif
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_CONS_INDEX 1
+#define CONFIG_BAUDRATE 115200
+
+/* Command definition */
+#define CONFIG_CMD_BMODE
+#define CONFIG_CMD_BOOTZ
+#undef CONFIG_CMD_IMLS
+
+#define CONFIG_LOADADDR 0x12000000
+#define CONFIG_SYS_TEXT_BASE 0x17800000
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "script=boot.scr\0" \
+ "image=/boot/uImage\0" \
+ "uboot=u-boot.imx\0" \
+ "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \
+ "fdt_addr=0x18000000\0" \
+ "boot_fdt=yes\0" \
+ "ip_dyn=yes\0" \
+ "console=" CONFIG_CONSOLE_DEV "\0" \
+ "fdt_high=0xffffffff\0" \
+ "initrd_high=0xffffffff\0" \
+ "sddev=0\0" \
+ "emmcdev=1\0" \
+ "partnum=1\0" \
+ "update_sd_firmware=" \
+ "if test ${ip_dyn} = yes; then " \
+ "setenv get_cmd dhcp; " \
+ "else " \
+ "setenv get_cmd tftp; " \
+ "fi; " \
+ "if mmc dev ${mmcdev}; then " \
+ "if ${get_cmd} ${update_sd_firmware_filename}; then " \
+ "setexpr fw_sz ${filesize} / 0x200; " \
+ "setexpr fw_sz ${fw_sz} + 1; " \
+ "mmc write ${loadaddr} 0x2 ${fw_sz}; " \
+ "fi; " \
+ "fi\0" \
+ "update_sf_uboot=" \
+ "if tftp $loadaddr $uboot; then " \
+ "sf probe; " \
+ "sf erase 0 0xC0000; " \
+ "sf write $loadaddr 0x400 $filesize; " \
+ "echo 'U-Boot upgraded. Please reset'; " \
+ "fi\0" \
+ "setargs=setenv bootargs console=${console},${baudrate} " \
+ "root=/dev/${rootdev} rw rootwait cma=128M\0" \
+ "loadbootscript=" \
+ "ext2load ${dev} ${devnum}:${partnum} ${loadaddr} ${script};\0" \
+ "bootscript=echo Running bootscript from ${dev}:${devnum}:${partnum};" \
+ " source\0" \
+ "loadimage=" \
+ "ext2load ${dev} ${devnum}:${partnum} ${loadaddr} ${image}\0" \
+ "loadfdt=ext2load ${dev} ${devnum}:${partnum} ${fdt_addr} ${fdt_file}\0" \
+ "tryboot=" \
+ "if run loadbootscript; then " \
+ "run bootscript; " \
+ "else " \
+ "if run loadimage; then " \
+ "run doboot; " \
+ "fi; " \
+ "fi;\0" \
+ "doboot=echo Booting from ${dev}:${devnum}:${partnum} ...; " \
+ "run setargs; " \
+ "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+ "if run loadfdt; then " \
+ "bootm ${loadaddr} - ${fdt_addr}; " \
+ "else " \
+ "if test ${boot_fdt} = try; then " \
+ "bootm; " \
+ "else " \
+ "echo WARN: Cannot load the DT; " \
+ "fi; " \
+ "fi; " \
+ "else " \
+ "bootm; " \
+ "fi;\0" \
+ "netargs=setenv bootargs console=${console},${baudrate} " \
+ "root=/dev/nfs " \
+ "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
+ "netboot=echo Booting from net ...; " \
+ "run netargs; " \
+ "if test ${ip_dyn} = yes; then " \
+ "setenv get_cmd dhcp; " \
+ "else " \
+ "setenv get_cmd tftp; " \
+ "fi; " \
+ "${get_cmd} ${image}; " \
+ "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+ "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
+ "bootm ${loadaddr} - ${fdt_addr}; " \
+ "else " \
+ "if test ${boot_fdt} = try; then " \
+ "bootm; " \
+ "else " \
+ "echo WARN: Cannot load the DT; " \
+ "fi; " \
+ "fi; " \
+ "else " \
+ "bootm; " \
+ "fi;\0" \
+
+#define CONFIG_BOOTCOMMAND \
+ "usb start; " \
+ "setenv dev usb; " \
+ "setenv devnum 0; " \
+ "setenv rootdev sda1; " \
+ "run tryboot; " \
+ \
+ "setenv dev mmc; " \
+ "setenv rootdev mmcblk0p1; " \
+ \
+ "setenv devnum ${sddev}; " \
+ "if mmc dev ${devnum}; then " \
+ "run tryboot; " \
+ "setenv rootdev mmcblk1p1; " \
+ "fi; " \
+ \
+ "setenv devnum ${emmcdev}; " \
+ "if mmc dev ${devnum}; then " \
+ "run tryboot; " \
+ "fi; " \
+ \
+ "bmode usb; " \
+
+#define CONFIG_ARP_TIMEOUT 200UL
+
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+#define CONFIG_AUTO_COMPLETE
+
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+
+#define CONFIG_SYS_MEMTEST_START 0x10000000
+#define CONFIG_SYS_MEMTEST_END 0x10010000
+#define CONFIG_SYS_MEMTEST_SCRATCH 0x10800000
+
+#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
+
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_STACKSIZE (128 * 1024)
+
+/* Physical Memory Map */
+#define CONFIG_NR_DRAM_BANKS 1
+#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
+
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
+#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+ (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+/* FLASH and environment organization */
+#define CONFIG_SYS_NO_FLASH
+
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_SIZE (8 * 1024)
+#define CONFIG_ENV_OFFSET (768 * 1024)
+#define CONFIG_ENV_SECT_SIZE (64 * 1024)
+#define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS
+#define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS
+#define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE
+#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
+
+#define CONFIG_OF_LIBFDT
+
+#ifndef CONFIG_SYS_DCACHE_OFF
+#define CONFIG_CMD_CACHE
+#endif
+
+#define CONFIG_SYS_FSL_USDHC_NUM 3
+
+/* Framebuffer */
+#define CONFIG_VIDEO
+#define CONFIG_VIDEO_IPUV3
+#define CONFIG_CFB_CONSOLE
+#define CONFIG_VGA_AS_SINGLE_DEVICE
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
+#define CONFIG_VIDEO_BMP_RLE8
+#define CONFIG_SPLASH_SCREEN
+#define CONFIG_SPLASH_SCREEN_ALIGN
+#define CONFIG_BMP_16BPP
+#define CONFIG_VIDEO_LOGO
+#define CONFIG_VIDEO_BMP_LOGO
+#define CONFIG_IPUV3_CLK 260000000
+#define CONFIG_IMX_HDMI
+#define CONFIG_IMX_VIDEO_SKIP
+
+#undef CONFIG_CMD_PCI
+#ifdef CONFIG_CMD_PCI
+#define CONFIG_PCI
+#define CONFIG_PCI_PNP
+#define CONFIG_PCI_SCAN_SHOW
+#define CONFIG_PCIE_IMX
+#define CONFIG_PCIE_IMX_PERST_GPIO IMX_GPIO_NR(7, 12)
+#define CONFIG_PCIE_IMX_POWER_GPIO IMX_GPIO_NR(1, 5)
+#endif
+
+/* I2C Configs */
+#define CONFIG_CMD_I2C
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_SPEED 100000
+#define CONFIG_SYS_I2C_MXC_I2C1
+#define CONFIG_SYS_I2C_MXC_I2C2
+#define CONFIG_SYS_I2C_MXC_I2C3
+
+#endif /* __GE_BX50V3_CONFIG_H */
#define CONFIG_CMD_MII
#define CONFIG_CMD_MMC
#define CONFIG_CMD_NAND
+#define CONFIG_CMD_NAND_TRIMFFS
#define CONFIG_CMD_PING
#define CONFIG_CMD_SATA
#define CONFIG_CMD_USB
#define CONFIG_CMD_CACHE
#define CONFIG_CMD_DATE
#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_EXT4
+#define CONFIG_CMD_EXT4_WRITE
#define CONFIG_CMD_FAT
+#define CONFIG_CMD_FS_GENERIC
#define CONFIG_CMD_MII
#define CONFIG_CMD_MMC
#define CONFIG_CMD_PING
#define CONFIG_ENV_IS_IN_MMC
#if defined(CONFIG_ENV_IS_IN_MMC)
-#define CONFIG_ENV_OFFSET (8 * 64 * 1024)
+#define CONFIG_ENV_OFFSET (768 * 1024)
#endif
/* Framebuffer */
/* Enable iomux-lpsr support */
#define CONFIG_IOMUX_LPSR
-#define CONFIG_IMX_FIXED_IVT_OFFSET
-
-/* Size of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN (32 * SZ_1M)
-
-#define CONFIG_BOARD_EARLY_INIT_F
-#define CONFIG_BOARD_LATE_INIT
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO
-#define CONFIG_FSL_CLK
-
#define CONFIG_LOADADDR 0x80800000
#define CONFIG_SYS_TEXT_BASE 0x87800000
/* UART */
#define CONFIG_MXC_UART
-#define CONFIG_MXC_UART_BASE UART1_IPS_BASE_ADDR
/* MMC */
#define CONFIG_MMC
#define CONFIG_DBG_MONITOR
#define PHYS_SDRAM_SIZE SZ_1G
+#define CONFIG_MXC_UART_BASE UART1_IPS_BASE_ADDR
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN (32 * SZ_1M)
+
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_BOARD_LATE_INIT
+
/* Uncomment to enable secure boot support */
/* #define CONFIG_SECURE_BOOT */
#define CONFIG_CSF_SIZE 0x4000
--- /dev/null
+/*
+ * Copyright (C) 2016 NXP Semiconductors
+ *
+ * Configuration settings for the i.MX7S Warp board.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __WARP7_CONFIG_H
+#define __WARP7_CONFIG_H
+
+#define CONFIG_BOOTDELAY 1
+#include "mx7_common.h"
+
+#define PHYS_SDRAM_SIZE SZ_512M
+
+#define CONFIG_MXC_UART_BASE UART1_IPS_BASE_ADDR
+
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN (32 * SZ_1M)
+
+#define CONFIG_BOARD_EARLY_INIT_F
+
+/* MMC Config*/
+#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC3_BASE_ADDR
+#define CONFIG_SUPPORT_EMMC_BOOT
+#define CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE
+#define CONFIG_SYS_MMC_IMG_LOAD_PART 1
+
+#define CONFIG_DFU_ENV_SETTINGS \
+ "dfu_alt_info=image raw 0 0x800000;"\
+ "u-boot raw 0 0x4000;"\
+ "bootimg part 0 1;"\
+ "rootfs part 0 2\0" \
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ CONFIG_DFU_ENV_SETTINGS \
+ "script=boot.scr\0" \
+ "image=zImage\0" \
+ "console=ttymxc0\0" \
+ "fdt_high=0xffffffff\0" \
+ "initrd_high=0xffffffff\0" \
+ "fdt_file=imx7d-warp.dtb\0" \
+ "fdt_addr=0x83000000\0" \
+ "boot_fdt=try\0" \
+ "ip_dyn=yes\0" \
+ "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
+ "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
+ "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
+ "mmcargs=setenv bootargs console=${console},${baudrate} " \
+ "root=${mmcroot}\0" \
+ "loadbootscript=" \
+ "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
+ "bootscript=echo Running bootscript from mmc ...; " \
+ "source\0" \
+ "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
+ "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
+ "mmcboot=echo Booting from mmc ...; " \
+ "run mmcargs; " \
+ "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+ "if run loadfdt; then " \
+ "bootz ${loadaddr} - ${fdt_addr}; " \
+ "else " \
+ "if test ${boot_fdt} = try; then " \
+ "bootz; " \
+ "else " \
+ "echo WARN: Cannot load the DT; " \
+ "fi; " \
+ "fi; " \
+ "else " \
+ "bootz; " \
+ "fi;\0" \
+
+#define CONFIG_BOOTCOMMAND \
+ "mmc dev ${mmcdev};" \
+ "mmc dev ${mmcdev}; if mmc rescan; then " \
+ "if run loadbootscript; then " \
+ "run bootscript; " \
+ "else " \
+ "if run loadimage; then " \
+ "run mmcboot; " \
+ "fi; " \
+ "fi; " \
+ "fi"
+
+#define CONFIG_CMD_MEMTEST
+#define CONFIG_SYS_MEMTEST_START 0x80000000
+#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x20000000)
+
+#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
+#define CONFIG_SYS_HZ 1000
+
+#define CONFIG_STACKSIZE SZ_128K
+
+/* Physical Memory Map */
+#define CONFIG_NR_DRAM_BANKS 1
+#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
+
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
+#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+ (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+/* FLASH and environment organization */
+#define CONFIG_SYS_NO_FLASH
+#define CONFIG_ENV_SIZE SZ_8K
+#define CONFIG_ENV_IS_IN_MMC
+
+#define CONFIG_ENV_OFFSET (8 * SZ_64K)
+#define CONFIG_SYS_FSL_USDHC_NUM 1
+
+#define CONFIG_SYS_MMC_ENV_DEV 0
+#define CONFIG_SYS_MMC_ENV_PART 0
+#define CONFIG_MMCROOT "/dev/mmcblk2p2"
+
+/* USB Configs */
+#define CONFIG_CMD_USB
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_MX7
+#define CONFIG_USB_STORAGE
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+
+#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
+#define CONFIG_MXC_USB_FLAGS 0
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 /* Only OTG1 port enabled */
+
+#define CONFIG_IMX_THERMAL
+
+#define CONFIG_CI_UDC
+#define CONFIG_USBD_HS
+#define CONFIG_USB_GADGET_DUALSPEED
+
+#define CONFIG_USB_GADGET
+#define CONFIG_CMD_USB_MASS_STORAGE
+#define CONFIG_USB_FUNCTION_MASS_STORAGE
+#define CONFIG_USB_GADGET_DOWNLOAD
+#define CONFIG_USB_GADGET_VBUS_DRAW 2
+
+#define CONFIG_G_DNL_VENDOR_NUM 0x0525
+#define CONFIG_G_DNL_PRODUCT_NUM 0xa4a5
+#define CONFIG_G_DNL_MANUFACTURER "FSL"
+
+/* USB Device Firmware Update support */
+#define CONFIG_CMD_DFU
+#define CONFIG_USB_FUNCTION_DFU
+#define CONFIG_DFU_MMC
+#define CONFIG_SYS_DFU_DATA_BUF_SIZE SZ_16M
+#define DFU_DEFAULT_POLL_TIMEOUT 300
+
+#endif
--- /dev/null
+/*
+ * Copyright (C) 2015-2016 Stefan Roese <sr@denx.de>
+ *
+ * Configuration settings for the CCV xPress board
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#ifndef __XPRESS_CONFIG_H
+#define __XPRESS_CONFIG_H
+
+#include "mx6_common.h"
+#include <asm/imx-common/gpio.h>
+
+/* SPL options */
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_MMC_SUPPORT
+#include "imx6_spl.h"
+
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN (16 << 20)
+
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_BOARD_LATE_INIT
+
+#define CONFIG_MXC_UART
+#define CONFIG_MXC_UART_BASE UART1_BASE
+
+/* MMC Configs */
+#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR
+#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */
+
+/* I2C configs */
+#define CONFIG_CMD_I2C
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
+#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
+#define CONFIG_SYS_I2C_MXC_I2C4 /* enable I2C bus 4 */
+#define CONFIG_SYS_I2C_SPEED 100000
+
+/* Miscellaneous configurable options */
+#define CONFIG_CMD_MEMTEST
+#define CONFIG_SYS_MEMTEST_START 0x80000000
+#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x10000000)
+
+#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
+#define CONFIG_SYS_HZ 1000
+
+#define CONFIG_SYS_CONSOLE_INFO_QUIET
+#define CONFIG_CMDLINE_EDITING
+
+/* Physical Memory Map */
+#define CONFIG_NR_DRAM_BANKS 1
+#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
+#define PHYS_SDRAM_SIZE (128 << 20)
+
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
+#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+ (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+/* FLASH and environment organization */
+#define CONFIG_SYS_NO_FLASH
+
+/* Environment is in stored in the eMMC boot partition */
+#define CONFIG_ENV_SIZE (16 << 10)
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_ENV_OFFSET (512 << 10)
+#define CONFIG_SYS_MMC_ENV_DEV 0 /* USDHC2 */
+#define CONFIG_SYS_MMC_ENV_PART 1 /* boot parition */
+#define CONFIG_MMCROOT "/dev/mmcblk0p2" /* USDHC2 */
+
+#define CONFIG_OF_LIBFDT
+#define CONFIG_CMD_BOOTZ
+#define CONFIG_CMD_BMODE
+#define CONFIG_CMD_CACHE
+
+/* USB Configs */
+#define CONFIG_CMD_USB
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_MX6
+#define CONFIG_USB_STORAGE
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
+#define CONFIG_MXC_USB_FLAGS 0
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
+
+#define CONFIG_FEC_MXC
+#define CONFIG_MII
+#define CONFIG_CMD_MII
+#define CONFIG_FEC_ENET_DEV 0
+#define IMX_FEC_BASE ENET_BASE_ADDR
+#define CONFIG_FEC_MXC_PHYADDR 0x0
+#define CONFIG_FEC_XCV_TYPE RMII
+#define CONFIG_ETHPRIME "FEC"
+#define CONFIG_PHYLIB
+#define CONFIG_PHY_SMSC
+
+#define CONFIG_IMX_THERMAL
+
+#define CONFIG_SYS_MMC_IMG_LOAD_PART 1
+
+#define CONFIG_UBOOT_SECTOR_START 0x2
+#define CONFIG_UBOOT_SECTOR_COUNT 0x3fe
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "script=boot.scr\0" \
+ "image=zImage\0" \
+ "console=ttymxc0\0" \
+ "fdt_high=0xffffffff\0" \
+ "initrd_high=0xffffffff\0" \
+ "fdt_file=undefined\0" \
+ "fdt_addr=0x83000000\0" \
+ "boot_fdt=try\0" \
+ "ip_dyn=yes\0" \
+ "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
+ "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
+ "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
+ "mmcautodetect=yes\0" \
+ "mmcargs=setenv bootargs console=${console},${baudrate} " \
+ "root=${mmcroot}\0" \
+ "loadbootscript=" \
+ "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
+ "bootscript=echo Running bootscript from mmc ...; " \
+ "source\0" \
+ "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
+ "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
+ "mmcboot=echo Booting from mmc ...; " \
+ "run mmcargs; " \
+ "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+ "if run loadfdt; then " \
+ "bootz ${loadaddr} - ${fdt_addr}; " \
+ "else " \
+ "if test ${boot_fdt} = try; then " \
+ "bootz; " \
+ "else " \
+ "echo WARN: Cannot load the DT; " \
+ "fi; " \
+ "fi; " \
+ "else " \
+ "bootz; " \
+ "fi;\0" \
+ "uboot=ccv/u-boot.imx\0" \
+ "uboot_start="__stringify(CONFIG_UBOOT_SECTOR_START)"\0" \
+ "uboot_size="__stringify(CONFIG_UBOOT_SECTOR_COUNT)"\0" \
+ "update_uboot=if tftp ${uboot}; then " \
+ "if itest ${filesize} > 0; then " \
+ "mmc dev 0 1;" \
+ "setexpr blkc ${filesize} / 0x200;" \
+ "setexpr blkc ${blkc} + 1;" \
+ "if itest ${blkc} <= ${uboot_size}; then " \
+ "mmc write ${loadaddr} ${uboot_start} " \
+ "${blkc};" \
+ "fi;" \
+ "fi; fi;" \
+ "setenv filesize; setenv blkc\0" \
+ "update_bootpart=mmc bootbus 0 2 1 2;mmc partconf 0 1 1 0\0"
+
+#endif /* __XPRESS_CONFIG_H */
projects / karo-tx-uboot.git / commitdiff