{ PINMUX_CFG_REG_VAR("MOD_SEL2", 0xE6060094, 32,
3, 1, 1, 1, 2, 1, 2, 1, 2,
1, 1, 1, 3, 3, 2, 3, 2, 2) {
- /* RESEVED [3] */
+ /* RESERVED [3] */
0, 0, 0, 0, 0, 0, 0, 0,
/* SEL_TMU1 [1] */
FN_SEL_TMU1_0, FN_SEL_TMU1_1,
FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1, FN_SEL_SCIFA2_2, 0,
/* SEL_CAN1 [1] */
FN_SEL_CAN1_0, FN_SEL_CAN1_1,
- /* RESEVED [2] */
+ /* RESERVED [2] */
0, 0, 0, 0,
- /* RESEVED [1] (actually TX2, RX2 vs. TX2_B, RX2_B of SCIF2) */
+ /* RESERVED [1] (actually TX2, RX2 vs. TX2_B, RX2_B of SCIF2) */
0, 0,
/* SEL_ADI [1] */
FN_SEL_ADI_0, FN_SEL_ADI_1,
FN_SEL_IICDVFS_0, FN_SEL_IICDVFS_1,
/* SEL_IIC0 [1] */
FN_SEL_IIC0_0, FN_SEL_IIC0_1,
- /* RESEVED [2] */
+ /* RESERVED [2] */
0, 0, 0, 0,
- /* RESEVED [4] */
+ /* RESERVED [4] */
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
- /* RESEVED [4] */
+ /* RESERVED [4] */
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
- /* RESEVED [2] */
+ /* RESERVED [2] */
0, 0, 0, 0,
/* SEL_IEB [2] */
FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2, 0,
- /* RESEVED [4] */
+ /* RESERVED [4] */
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
- /* RESEVED [2] */
+ /* RESERVED [2] */
0, 0, 0, 0,
/* SEL_IIC2 [3] */
FN_SEL_IIC2_0, FN_SEL_IIC2_1, FN_SEL_IIC2_2, FN_SEL_IIC2_3,