.ctrlbit = (1 << 1),
};
+static struct clk clk_mdma1 = {
+ .name = "dma",
+ .devname = "dma-pl330.2",
+ .enable = exynos4_clk_ip_image_ctrl,
+ .ctrlbit = ((1 << 8) | (1 << 5) | (1 << 2)),
+};
+
struct clk *clkset_group_list[] = {
[0] = &clk_ext_xtal_mux,
[1] = &clk_xusbxti,
static struct clk *clk_cdev[] = {
&clk_pdma0,
&clk_pdma1,
+ &clk_mdma1,
};
static struct clksrc_clk *clksrc_cdev[] = {
.periphid = 0x00041330,
};
+u8 mdma_peri[] = {
+ DMACH_MTOM_0,
+ DMACH_MTOM_1,
+ DMACH_MTOM_2,
+ DMACH_MTOM_3,
+ DMACH_MTOM_4,
+ DMACH_MTOM_5,
+ DMACH_MTOM_6,
+ DMACH_MTOM_7,
+};
+
+struct dma_pl330_platdata exynos4_mdma_pdata = {
+ .nr_valid_peri = ARRAY_SIZE(mdma_peri),
+ .peri_id = mdma_peri,
+};
+
+struct amba_device exynos4_device_mdma = {
+ .dev = {
+ .init_name = "dma-pl330.2",
+ .dma_mask = &dma_dmamask,
+ .coherent_dma_mask = DMA_BIT_MASK(32),
+ .platform_data = &exynos4_mdma_pdata,
+ },
+ .res = {
+ .start = EXYNOS4_PA_MDMA1,
+ .end = EXYNOS4_PA_MDMA1 + SZ_4K,
+ .flags = IORESOURCE_MEM,
+ },
+ .irq = {IRQ_MDMA1, NO_IRQ},
+ .periphid = 0x00041330,
+};
+
static int __init exynos4_dma_init(void)
{
if (of_have_populated_dt())
dma_cap_set(DMA_CYCLIC, exynos4_pdma1_pdata.cap_mask);
amba_device_register(&exynos4_device_pdma1, &iomem_resource);
+ dma_cap_set(DMA_MEMCPY, exynos4_mdma_pdata.cap_mask);
+ amba_device_register(&exynos4_device_mdma, &iomem_resource);
+
return 0;
}
arch_initcall(exynos4_dma_init);
#define IRQ_EINT15 IRQ_SPI(31)
#define IRQ_EINT16_31 IRQ_SPI(32)
+#define IRQ_MDMA0 IRQ_SPI(33)
+#define IRQ_MDMA1 IRQ_SPI(34)
#define IRQ_PDMA0 IRQ_SPI(35)
#define IRQ_PDMA1 IRQ_SPI(36)
#define IRQ_TIMER0_VIC IRQ_SPI(37)
#define EXYNOS4_PA_TWD 0x10500600
#define EXYNOS4_PA_L2CC 0x10502000
-#define EXYNOS4_PA_MDMA 0x10810000
+#define EXYNOS4_PA_MDMA0 0x10810000
+#define EXYNOS4_PA_MDMA1 0x12840000
#define EXYNOS4_PA_PDMA0 0x12680000
#define EXYNOS4_PA_PDMA1 0x12690000