drm/i915: fix to setup display reference clock control on Ironlake

commit c038e51e841581cc3fb9a76e5e16331331e9c85c upstream.

For new stepping of PCH, the display reference clock
is fully under driver's control. This one trys to setup
all needed reference clock for different outputs. Older
stepping of PCH chipset should be ignoring this.

This fixes output failure issue on newer PCH which requires
driver to take control of reference clock enabling.

Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Signed-off-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 7ef7e4d81d1e8535b0334166cc3f1cf9372e143b..dd14c27e806eefb6df053064a8df8f6c106e5cd9 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1990,11 +1990,11 @@
 #define  DREF_CPU_SOURCE_OUTPUT_MASK           (3<<13)
 #define  DREF_SSC_SOURCE_DISABLE                (0<<11)
 #define  DREF_SSC_SOURCE_ENABLE                 (2<<11)
-#define  DREF_SSC_SOURCE_MASK                  (2<<11)
+#define  DREF_SSC_SOURCE_MASK                  (3<<11)
 #define  DREF_NONSPREAD_SOURCE_DISABLE          (0<<9)
 #define  DREF_NONSPREAD_CK505_ENABLE           (1<<9)
 #define  DREF_NONSPREAD_SOURCE_ENABLE           (2<<9)
-#define  DREF_NONSPREAD_SOURCE_MASK            (2<<9)
+#define  DREF_NONSPREAD_SOURCE_MASK            (3<<9)
 #define  DREF_SUPERSPREAD_SOURCE_DISABLE        (0<<7)
 #define  DREF_SUPERSPREAD_SOURCE_ENABLE         (2<<7)
 #define  DREF_SSC4_DOWNSPREAD                   (0<<6)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 0fb177e7c8176979ce7bf1273a46a1bea77853d2..8f2cd74c575f5f636353448ee885495cae5e9bf4 100644 (file)
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2442,6 +2442,46 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
                                  link_bw, &m_n);
        }
 
+       /* Ironlake: try to setup display ref clock before DPLL
+        * enabling. This is only under driver's control after
+        * PCH B stepping, previous chipset stepping should be
+        * ignoring this setting.
+        */
+       if (IS_IGDNG(dev)) {
+               temp = I915_READ(PCH_DREF_CONTROL);
+               /* Always enable nonspread source */
+               temp &= ~DREF_NONSPREAD_SOURCE_MASK;
+               temp |= DREF_NONSPREAD_SOURCE_ENABLE;
+               I915_WRITE(PCH_DREF_CONTROL, temp);
+               POSTING_READ(PCH_DREF_CONTROL);
+
+               temp &= ~DREF_SSC_SOURCE_MASK;
+               temp |= DREF_SSC_SOURCE_ENABLE;
+               I915_WRITE(PCH_DREF_CONTROL, temp);
+               POSTING_READ(PCH_DREF_CONTROL);
+
+               udelay(200);
+
+               if (is_edp) {
+                       if (dev_priv->lvds_use_ssc) {
+                               temp |= DREF_SSC1_ENABLE;
+                               I915_WRITE(PCH_DREF_CONTROL, temp);
+                               POSTING_READ(PCH_DREF_CONTROL);
+
+                               udelay(200);
+
+                               temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
+                               temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
+                               I915_WRITE(PCH_DREF_CONTROL, temp);
+                               POSTING_READ(PCH_DREF_CONTROL);
+                       } else {
+                               temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
+                               I915_WRITE(PCH_DREF_CONTROL, temp);
+                               POSTING_READ(PCH_DREF_CONTROL);
+                       }
+               }
+       }
+
        if (IS_IGD(dev))
                fp = (1 << clock.n) << 16 | clock.m1 << 8 | clock.m2;
        else