MIPS: Probe the I6500 CPU

Introduce the I6500 PRID & probe it just the same way as I6400. The MIPS
I6500 is the latest in Imagination Technologies' I-Class range of CPUs,
with a focus on scalability & heterogeneity. It introduces the notion of
multiple clusters to the MIPS Coherent Processing System, allowing for a
far higher total number of cores & threads in a system when compared
with its predecessors. Clusters don't need to be identical, and may
contain differing numbers of cores & IOCUs, or cores with differing
properties.

This patch alone adds the basic support for booting Linux on an I6500
CPU without support for any of its new functionality, for which support
will be introduced in further patches.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/16190/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

diff --git a/arch/mips/include/asm/cpu-type.h b/arch/mips/include/asm/cpu-type.h
index bdd6dc18e65c618dc65bd8a487895386c8085eea..175fe565f4e1e6e078ead8d42da079cb779d7340 100644 (file)
--- a/arch/mips/include/asm/cpu-type.h
+++ b/arch/mips/include/asm/cpu-type.h
@@ -84,6 +84,7 @@ static inline int __pure __get_cpu_type(const int cpu_type)
 
 #ifdef CONFIG_SYS_HAS_CPU_MIPS64_R6
        case CPU_I6400:
+       case CPU_I6500:
        case CPU_P6600:
 #endif
 

diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h
index 98f59307e6a354ca5c61ada241aa010312d8c98c..3069359b01204a13638888c5c5fcfdec62c8c713 100644 (file)
--- a/arch/mips/include/asm/cpu.h
+++ b/arch/mips/include/asm/cpu.h
@@ -124,6 +124,7 @@
 #define PRID_IMP_P5600         0xa800
 #define PRID_IMP_I6400         0xa900
 #define PRID_IMP_M6250         0xab00
+#define PRID_IMP_I6500         0xb000
 
 /*
  * These are the PRID's for when 23:16 == PRID_COMP_SIBYTE
@@ -322,7 +323,7 @@ enum cpu_type_enum {
         */
        CPU_5KC, CPU_5KE, CPU_20KC, CPU_25KF, CPU_SB1, CPU_SB1A, CPU_LOONGSON2,
        CPU_LOONGSON3, CPU_CAVIUM_OCTEON, CPU_CAVIUM_OCTEON_PLUS,
-       CPU_CAVIUM_OCTEON2, CPU_CAVIUM_OCTEON3, CPU_XLR, CPU_XLP,
+       CPU_CAVIUM_OCTEON2, CPU_CAVIUM_OCTEON3, CPU_XLR, CPU_XLP, CPU_I6500,
 
        CPU_QEMU_GENERIC,
 

diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index 1aba27786bd5ae6cc38784c0f05f196745e1cd3d..353ade2c130a3ddce6e0fffb72063d9bf26dfacc 100644 (file)
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -564,6 +564,7 @@ static int set_ftlb_enable(struct cpuinfo_mips *c, enum ftlb_flags flags)
                back_to_back_c0_hazard();
                break;
        case CPU_I6400:
+       case CPU_I6500:
                /* There's no way to disable the FTLB */
                if (!(flags & FTLB_EN))
                        return 1;
@@ -1635,6 +1636,10 @@ static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu)
                c->cputype = CPU_I6400;
                __cpu_name[cpu] = "MIPS I6400";
                break;
+       case PRID_IMP_I6500:
+               c->cputype = CPU_I6500;
+               __cpu_name[cpu] = "MIPS I6500";
+               break;
        case PRID_IMP_M5150:
                c->cputype = CPU_M5150;
                __cpu_name[cpu] = "MIPS M5150";

diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
index 3fe99cb271a9cad44c55dfbf841b9de0e9093974..81d6a15c93d08ba2603d0e9f2dd8302546a97489 100644 (file)
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
@@ -1453,6 +1453,7 @@ static void probe_pcache(void)
        case CPU_20KC:
        case CPU_25KF:
        case CPU_I6400:
+       case CPU_I6500:
        case CPU_SB1:
        case CPU_SB1A:
        case CPU_XLR:
@@ -1512,6 +1513,7 @@ static void probe_pcache(void)
 
        case CPU_ALCHEMY:
        case CPU_I6400:
+       case CPU_I6500:
                c->icache.flags |= MIPS_CACHE_IC_F_DC;
                break;