drm/i915: add haswell_update_sprite_wm

On Haswell, whenever we change the sprites we need to completely
recalculate all the watermarks, because the sprites are one of the
parameters to the LP watermarks, so a change on the sprites may
trigger a change on which LP levels are enabled.

So on this commit we store all the parameters we need to store for
proper recalculation of the Haswell WMs and then call
haswell_update_wm.

Notice that for now our haswell_update_wm function is not really using
these parameters we're storing, but on the next commits we'll use
these parameters.

Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 3e6e5e7b089f5f9114091c34607e34dc363f4425..bb4c50b570850a72f186a45f4449af080c8cbf41 100644 (file)
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -326,6 +326,18 @@ struct intel_plane {
        unsigned int crtc_w, crtc_h;
        uint32_t src_x, src_y;
        uint32_t src_w, src_h;
+
+       /* Since we need to change the watermarks before/after
+        * enabling/disabling the planes, we need to store the parameters here
+        * as the other pieces of the struct may not reflect the values we want
+        * for the watermark calculations. Currently only Haswell uses this.
+        */
+       struct {
+               bool enable;
+               uint8_t bytes_per_pixel;
+               uint32_t horiz_pixels;
+       } wm;
+
        void (*update_plane)(struct drm_plane *plane,
                             struct drm_framebuffer *fb,
                             struct drm_i915_gem_object *obj,

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 3515efd049dd7853e4616ad14a829e9c3f784e00..9328ed98ce2fddb68deaee7d9b5f860a4196425b 100644 (file)
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -2118,6 +2118,26 @@ static void haswell_update_wm(struct drm_device *dev)
        sandybridge_update_wm(dev);
 }
 
+static void haswell_update_sprite_wm(struct drm_device *dev, int pipe,
+                                    uint32_t sprite_width, int pixel_size,
+                                    bool enable)
+{
+       struct drm_plane *plane;
+
+       list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
+               struct intel_plane *intel_plane = to_intel_plane(plane);
+
+               if (intel_plane->pipe == pipe) {
+                       intel_plane->wm.enable = enable;
+                       intel_plane->wm.horiz_pixels = sprite_width + 1;
+                       intel_plane->wm.bytes_per_pixel = pixel_size;
+                       break;
+               }
+       }
+
+       haswell_update_wm(dev);
+}
+
 static bool
 sandybridge_compute_sprite_wm(struct drm_device *dev, int plane,
                              uint32_t sprite_width, int pixel_size,
@@ -4631,7 +4651,8 @@ void intel_init_pm(struct drm_device *dev)
                } else if (IS_HASWELL(dev)) {
                        if (I915_READ64(MCH_SSKPD)) {
                                dev_priv->display.update_wm = haswell_update_wm;
-                               dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
+                               dev_priv->display.update_sprite_wm =
+                                       haswell_update_sprite_wm;
                        } else {
                                DRM_DEBUG_KMS("Failed to read display plane latency. "
                                              "Disable CxSR\n");