drm/i915/fbc: Allow on unfenced surfaces, for recent gen

Only fbc1 is tied to using a fence. Later iterations of fbc are more
flexible and allow operation on unfenced frontbuffers.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Daniel Vetter <daniel.vetter@intel.com>
Cc: "Zanoni, Paulo R" <paulo.r.zanoni@intel.com>
Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/20160819155428.1670-3-chris@chris-wilson.co.uk

diff --git a/drivers/gpu/drm/i915/intel_fbc.c b/drivers/gpu/drm/i915/intel_fbc.c
index faa67624e1ed734b80b0c0b9734b63c173d9389c..bf8b22ad9aed854d2f7ce79a45ac85ec1857ad2a 100644 (file)
--- a/drivers/gpu/drm/i915/intel_fbc.c
+++ b/drivers/gpu/drm/i915/intel_fbc.c
@@ -799,8 +799,10 @@ static bool intel_fbc_can_activate(struct intel_crtc *crtc)
         */
        if (cache->fb.tiling_mode != I915_TILING_X ||
            cache->fb.fence_reg == I915_FENCE_REG_NONE) {
-               fbc->no_fbc_reason = "framebuffer not tiled or fenced";
-               return false;
+               if (INTEL_GEN(dev_priv) < 5) {
+                       fbc->no_fbc_reason = "framebuffer not tiled or fenced";
+                       return false;
+               }
        }
        if (INTEL_INFO(dev_priv)->gen <= 4 && !IS_G4X(dev_priv) &&
            cache->plane.rotation != DRM_ROTATE_0) {