mips: mt7620: fallback to SDRAM when syscfg0 does not have a valid value for the...

Mediatek MT7620 SoC has syscfg0 bits where it sets the type of memory being used.
However, sometimes those bits are not set properly (reading "11"). In this case, the SoC assumes SDRAM.
The patch below reflects that.

Signed-off-by: Sashka Nochkin <linux-mips@durdom.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/13135/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

diff --git a/arch/mips/include/asm/mach-ralink/mt7620.h b/arch/mips/include/asm/mach-ralink/mt7620.h
index ece7420f6562979bfeb8297dd2f5095dc20d9794..a73350b07fdf0bca66443d480ff2139def92c758 100644 (file)
--- a/arch/mips/include/asm/mach-ralink/mt7620.h
+++ b/arch/mips/include/asm/mach-ralink/mt7620.h
@@ -72,6 +72,7 @@
 #define SYSCFG0_DRAM_TYPE_SDRAM                0
 #define SYSCFG0_DRAM_TYPE_DDR1         1
 #define SYSCFG0_DRAM_TYPE_DDR2         2
+#define SYSCFG0_DRAM_TYPE_UNKNOWN      3
 
 #define SYSCFG0_DRAM_TYPE_DDR2_MT7628  0
 #define SYSCFG0_DRAM_TYPE_DDR1_MT7628  1

diff --git a/arch/mips/ralink/mt7620.c b/arch/mips/ralink/mt7620.c
index 2c623f6bca084f75163caa0fb79a0f24c43494f1..88b82fe21ae6a9370ab36cfed3d6e350671dfcce 100644 (file)
--- a/arch/mips/ralink/mt7620.c
+++ b/arch/mips/ralink/mt7620.c
@@ -581,11 +581,14 @@ void prom_soc_init(struct ralink_soc_info *soc_info)
                (rev & CHIP_REV_ECO_MASK));
 
        cfg0 = __raw_readl(sysc + SYSC_REG_SYSTEM_CONFIG0);
-       if (is_mt76x8())
+       if (is_mt76x8()) {
                dram_type = cfg0 & DRAM_TYPE_MT7628_MASK;
-       else
+       } else {
                dram_type = (cfg0 >> SYSCFG0_DRAM_TYPE_SHIFT) &
                            SYSCFG0_DRAM_TYPE_MASK;
+               if (dram_type == SYSCFG0_DRAM_TYPE_UNKNOWN)
+                       dram_type = SYSCFG0_DRAM_TYPE_SDRAM;
+       }
 
        soc_info->mem_base = MT7620_DRAM_BASE;
        if (is_mt76x8())