This fixes the "not syncing: Could not identify cpu/level ..." panic
when a PCI irq is requested the second time.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
struct bridge_controller *bc = IRQ_TO_BRIDGE(irq);
struct hub_data *hub = hub_data(cpu_to_node(bc->irq_cpu));
bridge_t *bridge = bc->base;
- struct slice_data *si = cpu_data[bc->irq_cpu].data;
int pin, swlevel;
cpuid_t cpu;
intr_disconnect_level(cpu, swlevel);
__clear_bit(swlevel, hub->irq_alloc_mask);
- si->level_to_irq[swlevel] = -1;
bridge->b_int_enable &= ~(1 << pin);
bridge->b_wid_tflush;