Currently, S5P_TIMER_IRQ is based at the end of VICs. This patch changes
the S5P_TIMER_IRQ base from end of VICs to 11 in ISA IRQ space.
No of VICs varies between SOCs. This causes an exception on S5P6442.
Signed-off-by: Atul Dahiya <atul.dahiya@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
#define S5P_IRQ_VIC0(x) (S5P_VIC0_BASE + (x))
#define S5P_IRQ_VIC1(x) (S5P_VIC1_BASE + (x))
-#define S5P_TIMER_IRQ(x) S5P_IRQ(64 + (x))
+#define S5P_TIMER_IRQ(x) S5P_IRQ(11 + (x))
#define IRQ_TIMER0 S5P_TIMER_IRQ(0)
#define IRQ_TIMER1 S5P_TIMER_IRQ(1)