Merge branch 'treewide/cleanup' into next/soc

Merge in cleanup to avoid internal conflicts with newly added code.

* treewide/cleanup:
  ARM: use "depends on" for SoC configs instead of "if" after prompt
  ARM/clocksource: use automatic DT probing for ux500 PRCMU
  ARM: use const and __initconst for smp_operations
  ARM: hisi: do not export smp_operations structures

Signed-off-by: Olof Johansson <olof@lixom.net>

diff --cc arch/arm/mach-bcm/Kconfig
index 0207736674d6bbc2099d367e6e658e1bb1fcdee9,77116dcac01a10e1028a4d6e21cbb5359f2322e0..c9723d82cb301c26f4e66dfbfe36adeaac2b3177
--- 1/arch/arm/mach-bcm/Kconfig
--- 2/arch/arm/mach-bcm/Kconfig
+++ b/arch/arm/mach-bcm/Kconfig
@@@ -52,13 -53,9 +55,14 @@@ config ARCH_BCM_NS
          NAND flash, SATA and several other IO controllers.
  
  config ARCH_BCM_5301X
-       bool "Broadcom BCM470X / BCM5301X ARM SoC" if ARCH_MULTI_V7
+       bool "Broadcom BCM470X / BCM5301X ARM SoC"
+       depends on ARCH_MULTI_V7
        select ARCH_BCM_IPROC
 +      select ARM_ERRATA_754322
 +      select ARM_ERRATA_775420
 +      select ARM_ERRATA_764369 if SMP
 +      select HAVE_SMP
 +
        help
          Support for Broadcom BCM470X and BCM5301X SoCs with ARM CPU cores.
  

diff --cc arch/arm/mach-bcm/platsmp.c
index ea4201e6d0c956cf14eb973e98fadcd97281ecdf,da8328b97b7dc1616e04df2e9a30f1471f69ef26..575defcc53f932f9af463805dc88cf327802df2e
--- 1/arch/arm/mach-bcm/platsmp.c
--- 2/arch/arm/mach-bcm/kona_smp.c
+++ b/arch/arm/mach-bcm/platsmp.c
@@@ -252,33 -191,12 +252,33 @@@ static int kona_boot_secondary(unsigne
  
        pr_err("timeout waiting for cpu %u to start\n", cpu_id);
  
 -      return -ENOSYS;
 +      return -ENXIO;
 +}
 +
 +static int nsp_boot_secondary(unsigned int cpu, struct task_struct *idle)
 +{
 +      int ret;
 +
 +      /*
 +       * After wake up, secondary core branches to the startup
 +       * address programmed at SKU ROM LUT location.
 +       */
 +      ret = nsp_write_lut();
 +      if (ret) {
 +              pr_err("unable to write startup addr to SKU ROM LUT\n");
 +              goto out;
 +      }
 +
 +      /* Send a CPU wakeup interrupt to the secondary core */
 +      arch_send_wakeup_ipi_mask(cpumask_of(cpu));
 +
 +out:
 +      return ret;
  }
  
- static struct smp_operations bcm_smp_ops __initdata = {
+ static const struct smp_operations bcm_smp_ops __initconst = {
        .smp_prepare_cpus       = bcm_smp_prepare_cpus,
 -      .smp_boot_secondary     = bcm_boot_secondary,
 +      .smp_boot_secondary     = kona_boot_secondary,
  };
  CPU_METHOD_OF_DECLARE(bcm_smp_bcm281xx, "brcm,bcm11351-cpu-method",
                        &bcm_smp_ops);

diff --cc arch/arm/mach-exynos/Kconfig
Simple merge

diff --cc arch/arm/mach-rockchip/platsmp.c
index 9a5b2e0502f360d51c4a7e93456461f4314bedad,938888fc55a160dc6543af8f22f6349a8661b35a..d42a07e334822bfabbda05e3fa8f2dbe0c3a2093
--- 1/arch/arm/mach-rockchip/platsmp.c
--- 2/arch/arm/mach-rockchip/platsmp.c
+++ b/arch/arm/mach-rockchip/platsmp.c
@@@ -351,16 -340,7 +351,16 @@@ static void rockchip_cpu_die(unsigned i
  }
  #endif
  
- static struct smp_operations rockchip_smp_ops __initdata = {
 +static const struct smp_operations rk3036_smp_ops __initconst = {
 +      .smp_prepare_cpus       = rk3036_smp_prepare_cpus,
 +      .smp_boot_secondary     = rockchip_boot_secondary,
 +#ifdef CONFIG_HOTPLUG_CPU
 +      .cpu_kill               = rockchip_cpu_kill,
 +      .cpu_die                = rockchip_cpu_die,
 +#endif
 +};
 +
+ static const struct smp_operations rockchip_smp_ops __initconst = {
        .smp_prepare_cpus       = rockchip_smp_prepare_cpus,
        .smp_boot_secondary     = rockchip_boot_secondary,
  #ifdef CONFIG_HOTPLUG_CPU

diff --cc arch/arm/mach-zynq/Kconfig
index 77d7df75e2a037a600c0091a9751b99532274066,f287667e4fc501835d6518da3e6e6b9b347011b4..fd0aeeb098817fbd5c715b71a0c898ceae9e4840
--- 1/arch/arm/mach-zynq/Kconfig
--- 2/arch/arm/mach-zynq/Kconfig
+++ b/arch/arm/mach-zynq/Kconfig
@@@ -1,6 -1,6 +1,7 @@@
  config ARCH_ZYNQ
-       bool "Xilinx Zynq ARM Cortex A9 Platform" if ARCH_MULTI_V7
+       bool "Xilinx Zynq ARM Cortex A9 Platform"
+       depends on ARCH_MULTI_V7
 +      select ARCH_HAS_RESET_CONTROLLER
        select ARCH_SUPPORTS_BIG_ENDIAN
        select ARM_AMBA
        select ARM_GIC