]> git.karo-electronics.de Git - karo-tx-linux.git/commitdiff
powerpc/85xx: Change deprecated binding for 85xx-based boards
authorBradley Hughes <bhughes@silicontkx.com>
Wed, 21 Jul 2010 12:04:06 +0000 (12:04 +0000)
committerKumar Gala <galak@kernel.crashing.org>
Wed, 4 Aug 2010 19:22:04 +0000 (14:22 -0500)
The "fsl,85..." style compatible binding was to be deprecated
some time ago.  This patch corrects existing occurrences of
the incorrect binding.  The memory-controller and
l2-cache-controller are the only affected nodes.

Signed-off-by: Bradley Hughes <bhughes@silicontkx.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
arch/powerpc/boot/dts/mpc8540ads.dts
arch/powerpc/boot/dts/mpc8541cds.dts
arch/powerpc/boot/dts/mpc8544ds.dts
arch/powerpc/boot/dts/mpc8548cds.dts
arch/powerpc/boot/dts/mpc8555cds.dts
arch/powerpc/boot/dts/mpc8560ads.dts
arch/powerpc/boot/dts/mpc8568mds.dts

index 9dc292962a9a395a6b6f6daace2313f1258720c8..8d1bf0fd9268eb787839b249a31afd2d59588861 100644 (file)
                };
 
                memory-controller@2000 {
-                       compatible = "fsl,8540-memory-controller";
+                       compatible = "fsl,mpc8540-memory-controller";
                        reg = <0x2000 0x1000>;
                        interrupt-parent = <&mpic>;
                        interrupts = <18 2>;
                };
 
                L2: l2-cache-controller@20000 {
-                       compatible = "fsl,8540-l2-cache-controller";
+                       compatible = "fsl,mpc8540-l2-cache-controller";
                        reg = <0x20000 0x1000>;
                        cache-line-size = <32>; // 32 bytes
                        cache-size = <0x40000>; // L2, 256K
index 9a3ad311aedfc62402338cf470a2373417332307..87ff96549fac14dd99ddaa66e276c8aac56aaf49 100644 (file)
                };
 
                memory-controller@2000 {
-                       compatible = "fsl,8541-memory-controller";
+                       compatible = "fsl,mpc8541-memory-controller";
                        reg = <0x2000 0x1000>;
                        interrupt-parent = <&mpic>;
                        interrupts = <18 2>;
                };
 
                L2: l2-cache-controller@20000 {
-                       compatible = "fsl,8541-l2-cache-controller";
+                       compatible = "fsl,mpc8541-l2-cache-controller";
                        reg = <0x20000 0x1000>;
                        cache-line-size = <32>; // 32 bytes
                        cache-size = <0x40000>; // L2, 256K
index 98e94b465662c4dfef1b8a8805721251eb157078..d793968743c9531e8157cc8cfabfd0eae7be9969 100644 (file)
                };
 
                memory-controller@2000 {
-                       compatible = "fsl,8544-memory-controller";
+                       compatible = "fsl,mpc8544-memory-controller";
                        reg = <0x2000 0x1000>;
                        interrupt-parent = <&mpic>;
                        interrupts = <18 2>;
                };
 
                L2: l2-cache-controller@20000 {
-                       compatible = "fsl,8544-l2-cache-controller";
+                       compatible = "fsl,mpc8544-l2-cache-controller";
                        reg = <0x20000 0x1000>;
                        cache-line-size = <32>; // 32 bytes
                        cache-size = <0x40000>; // L2, 256K
index 0f5262452682ebf6e25719b90efee5f6d5a92aa4..a17a5572fb7317eaa94e3bc37b44fac603a7e359 100644 (file)
                };
 
                memory-controller@2000 {
-                       compatible = "fsl,8548-memory-controller";
+                       compatible = "fsl,mpc8548-memory-controller";
                        reg = <0x2000 0x1000>;
                        interrupt-parent = <&mpic>;
                        interrupts = <18 2>;
                };
 
                L2: l2-cache-controller@20000 {
-                       compatible = "fsl,8548-l2-cache-controller";
+                       compatible = "fsl,mpc8548-l2-cache-controller";
                        reg = <0x20000 0x1000>;
                        cache-line-size = <32>; // 32 bytes
                        cache-size = <0x80000>; // L2, 512K
index 065b2f093de2527e60aef62abd9079bbcf9a5d16..5c5614f9eb17354aa1bba3b20998391cbb8d0a4c 100644 (file)
                };
 
                memory-controller@2000 {
-                       compatible = "fsl,8555-memory-controller";
+                       compatible = "fsl,mpc8555-memory-controller";
                        reg = <0x2000 0x1000>;
                        interrupt-parent = <&mpic>;
                        interrupts = <18 2>;
                };
 
                L2: l2-cache-controller@20000 {
-                       compatible = "fsl,8555-l2-cache-controller";
+                       compatible = "fsl,mpc8555-l2-cache-controller";
                        reg = <0x20000 0x1000>;
                        cache-line-size = <32>; // 32 bytes
                        cache-size = <0x40000>; // L2, 256K
index a5bb1ec70a5ac5805bd8c63dbaea192d995d498f..6e85e1ba08514edaa63eacaec208359b6b3773bb 100644 (file)
                };
 
                memory-controller@2000 {
-                       compatible = "fsl,8540-memory-controller";
+                       compatible = "fsl,mpc8540-memory-controller";
                        reg = <0x2000 0x1000>;
                        interrupt-parent = <&mpic>;
                        interrupts = <18 2>;
                };
 
                L2: l2-cache-controller@20000 {
-                       compatible = "fsl,8540-l2-cache-controller";
+                       compatible = "fsl,mpc8540-l2-cache-controller";
                        reg = <0x20000 0x1000>;
                        cache-line-size = <32>; // 32 bytes
                        cache-size = <0x40000>; // L2, 256K
index 92fb17876e7dbdfb483d1fd579b6800b3a982d46..30cf0e098bb96f9d1aaa70c56a12fccabe17b694 100644 (file)
                };
 
                memory-controller@2000 {
-                       compatible = "fsl,8568-memory-controller";
+                       compatible = "fsl,mpc8568-memory-controller";
                        reg = <0x2000 0x1000>;
                        interrupt-parent = <&mpic>;
                        interrupts = <18 2>;
                };
 
                L2: l2-cache-controller@20000 {
-                       compatible = "fsl,8568-l2-cache-controller";
+                       compatible = "fsl,mpc8568-l2-cache-controller";
                        reg = <0x20000 0x1000>;
                        cache-line-size = <32>; // 32 bytes
                        cache-size = <0x80000>; // L2, 512K