drm/armada: move plane state to struct armada_plane

Move more of the Armada plane state (source size, and displayed size and
position) into a state structure inside struct armada_plane.

Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>

diff --git a/drivers/gpu/drm/armada/armada_crtc.c b/drivers/gpu/drm/armada/armada_crtc.c
index 9ec7e6136bccb0aea81b55fd92830631d25305b9..719873be3beb07564786812df2da4ad11b43a8ad 100644 (file)
--- a/drivers/gpu/drm/armada/armada_crtc.c
+++ b/drivers/gpu/drm/armada/armada_crtc.c
@@ -543,6 +543,19 @@ static int armada_drm_crtc_mode_set(struct drm_crtc *crtc,
 
        interlaced = !!(adj->flags & DRM_MODE_FLAG_INTERLACE);
 
+       val = CFG_GRA_ENA | CFG_GRA_HSMOOTH;
+       val |= CFG_GRA_FMT(drm_fb_to_armada_fb(dcrtc->crtc.primary->fb)->fmt);
+       val |= CFG_GRA_MOD(drm_fb_to_armada_fb(dcrtc->crtc.primary->fb)->mod);
+
+       if (drm_fb_to_armada_fb(dcrtc->crtc.primary->fb)->fmt > CFG_420)
+               val |= CFG_PALETTE_ENA;
+
+       drm_to_armada_plane(crtc->primary)->state.ctrl0 = val;
+       drm_to_armada_plane(crtc->primary)->state.src_hw =
+       drm_to_armada_plane(crtc->primary)->state.dst_hw =
+               adj->crtc_hdisplay << 16 | adj->crtc_vdisplay;
+       drm_to_armada_plane(crtc->primary)->state.dst_yx = 0;
+
        i = armada_drm_crtc_calc_fb(dcrtc->crtc.primary->fb,
                                    x, y, regs, interlaced);
 
@@ -621,8 +634,12 @@ static int armada_drm_crtc_mode_set(struct drm_crtc *crtc,
        val = adj->crtc_vdisplay << 16 | adj->crtc_hdisplay;
 
        armada_reg_queue_set(regs, i, val, LCD_SPU_V_H_ACTIVE);
-       armada_reg_queue_set(regs, i, val, LCD_SPU_GRA_HPXL_VLN);
-       armada_reg_queue_set(regs, i, val, LCD_SPU_GZM_HPXL_VLN);
+       armada_reg_queue_set(regs, i,
+                            drm_to_armada_plane(crtc->primary)->state.src_hw,
+                            LCD_SPU_GRA_HPXL_VLN);
+       armada_reg_queue_set(regs, i,
+                            drm_to_armada_plane(crtc->primary)->state.dst_hw,
+                            LCD_SPU_GZM_HPXL_VLN);
        armada_reg_queue_set(regs, i, (lm << 16) | rm, LCD_SPU_H_PORCH);
        armada_reg_queue_set(regs, i, dcrtc->v[0].spu_v_porch, LCD_SPU_V_PORCH);
        armada_reg_queue_set(regs, i, dcrtc->v[0].spu_v_h_total,
@@ -634,13 +651,7 @@ static int armada_drm_crtc_mode_set(struct drm_crtc *crtc,
                                     ADV_VSYNCOFFEN, LCD_SPU_ADV_REG);
        }
 
-       val = CFG_GRA_ENA | CFG_GRA_HSMOOTH;
-       val |= CFG_GRA_FMT(drm_fb_to_armada_fb(dcrtc->crtc.primary->fb)->fmt);
-       val |= CFG_GRA_MOD(drm_fb_to_armada_fb(dcrtc->crtc.primary->fb)->mod);
-
-       if (drm_fb_to_armada_fb(dcrtc->crtc.primary->fb)->fmt > CFG_420)
-               val |= CFG_PALETTE_ENA;
-
+       val = drm_to_armada_plane(crtc->primary)->state.ctrl0;
        if (interlaced)
                val |= CFG_GRA_FTOGGLE;
 

diff --git a/drivers/gpu/drm/armada/armada_crtc.h b/drivers/gpu/drm/armada/armada_crtc.h
index 04fdd22d483bd8e56787b95bbfcfc8b490f52e91..5b2b2c55589c5c985cd6e3401dbc0cba0d5d601f 100644 (file)
--- a/drivers/gpu/drm/armada/armada_crtc.h
+++ b/drivers/gpu/drm/armada/armada_crtc.h
@@ -41,10 +41,18 @@ struct armada_plane_work {
                                      struct armada_plane_work *);
 };
 
+struct armada_plane_state {
+       u32 src_hw;
+       u32 dst_hw;
+       u32 dst_yx;
+       u32 ctrl0;
+};
+
 struct armada_plane {
        struct drm_plane        base;
        wait_queue_head_t       frame_wait;
        struct armada_plane_work *work;
+       struct armada_plane_state state;
 };
 #define drm_to_armada_plane(p) container_of(p, struct armada_plane, base)
 

diff --git a/drivers/gpu/drm/armada/armada_overlay.c b/drivers/gpu/drm/armada/armada_overlay.c
index 94af7c93276eae705c7080c9e17d4af8d67d3383..5e979bbd5d6dc806beb0b585638ae1ef28bb5e90 100644 (file)
--- a/drivers/gpu/drm/armada/armada_overlay.c
+++ b/drivers/gpu/drm/armada/armada_overlay.c
@@ -33,10 +33,6 @@ struct armada_ovl_plane_properties {
 struct armada_ovl_plane {
        struct armada_plane base;
        struct drm_framebuffer *old_fb;
-       uint32_t src_hw;
-       uint32_t dst_hw;
-       uint32_t dst_yx;
-       uint32_t ctrl0;
        struct {
                struct armada_plane_work work;
                struct armada_regs regs[13];
@@ -148,22 +144,22 @@ armada_ovl_plane_update(struct drm_plane *plane, struct drm_crtc *crtc,
 
        /* FIXME: overlay on an interlaced display */
        /* Just updating the position/size? */
-       if (plane->fb == fb && dplane->ctrl0 == ctrl0) {
+       if (plane->fb == fb && dplane->base.state.ctrl0 == ctrl0) {
                val = (drm_rect_height(&src) & 0xffff0000) |
                      drm_rect_width(&src) >> 16;
-               dplane->src_hw = val;
+               dplane->base.state.src_hw = val;
                writel_relaxed(val, dcrtc->base + LCD_SPU_DMA_HPXL_VLN);
 
                val = drm_rect_height(&dest) << 16 | drm_rect_width(&dest);
-               dplane->dst_hw = val;
+               dplane->base.state.dst_hw = val;
                writel_relaxed(val, dcrtc->base + LCD_SPU_DZM_HPXL_VLN);
 
                val = dest.y1 << 16 | dest.x1;
-               dplane->dst_yx = val;
+               dplane->base.state.dst_yx = val;
                writel_relaxed(val, dcrtc->base + LCD_SPU_DMA_OVSA_HPXL_VLN);
 
                return 0;
-       } else if (~dplane->ctrl0 & ctrl0 & CFG_DMA_ENA) {
+       } else if (~dplane->base.state.ctrl0 & ctrl0 & CFG_DMA_ENA) {
                /* Power up the Y/U/V FIFOs on ENA 0->1 transitions */
                armada_updatel(0, CFG_PDWN16x66 | CFG_PDWN32x66,
                               dcrtc->base + LCD_SPU_SRAM_PARA1);
@@ -230,28 +226,28 @@ armada_ovl_plane_update(struct drm_plane *plane, struct drm_crtc *crtc,
        }
 
        val = (drm_rect_height(&src) & 0xffff0000) | drm_rect_width(&src) >> 16;
-       if (dplane->src_hw != val) {
-               dplane->src_hw = val;
+       if (dplane->base.state.src_hw != val) {
+               dplane->base.state.src_hw = val;
                armada_reg_queue_set(dplane->vbl.regs, idx, val,
                                     LCD_SPU_DMA_HPXL_VLN);
        }
 
        val = drm_rect_height(&dest) << 16 | drm_rect_width(&dest);
-       if (dplane->dst_hw != val) {
-               dplane->dst_hw = val;
+       if (dplane->base.state.dst_hw != val) {
+               dplane->base.state.dst_hw = val;
                armada_reg_queue_set(dplane->vbl.regs, idx, val,
                                     LCD_SPU_DZM_HPXL_VLN);
        }
 
        val = dest.y1 << 16 | dest.x1;
-       if (dplane->dst_yx != val) {
-               dplane->dst_yx = val;
+       if (dplane->base.state.dst_yx != val) {
+               dplane->base.state.dst_yx = val;
                armada_reg_queue_set(dplane->vbl.regs, idx, val,
                                     LCD_SPU_DMA_OVSA_HPXL_VLN);
        }
 
-       if (dplane->ctrl0 != ctrl0) {
-               dplane->ctrl0 = ctrl0;
+       if (dplane->base.state.ctrl0 != ctrl0) {
+               dplane->base.state.ctrl0 = ctrl0;
                armada_reg_queue_mod(dplane->vbl.regs, idx, ctrl0,
                        CFG_CBSH_ENA | CFG_DMAFORMAT | CFG_DMA_FTOGGLE |
                        CFG_DMA_HSMOOTH | CFG_DMA_TSTMODE |
@@ -282,7 +278,7 @@ static int armada_ovl_plane_disable(struct drm_plane *plane)
        armada_drm_crtc_plane_disable(dcrtc, plane);
 
        dcrtc->plane = NULL;
-       dplane->ctrl0 = 0;
+       dplane->base.state.ctrl0 = 0;
 
        fb = xchg(&dplane->old_fb, NULL);
        if (fb)