Merge branch 'mips-next-3.9' of git://git.linux-mips.org/pub/scm/john/linux-john...

diff --cc arch/mips/Kbuild.platforms
index 5c088494e0468ed0eb1cd2041c1a9f9e3867c1d2,9a73ce6f4c58d283a44ad365611e44d237687f73..4b597d91a8d5f2c44ed1f50ea0b11270d711f124
--- 1/arch/mips/Kbuild.platforms
--- 2/arch/mips/Kbuild.platforms
+++ b/arch/mips/Kbuild.platforms
@@@ -18,9 -18,11 +18,10 @@@ platforms += loongson
  platforms += mti-malta
  platforms += mti-sead3
  platforms += netlogic
 -platforms += pmc-sierra
 +platforms += pmcs-msp71xx
  platforms += pnx833x
 -platforms += pnx8550
  platforms += powertv
+ platforms += ralink
  platforms += rb532
  platforms += sgi-ip22
  platforms += sgi-ip27

diff --cc arch/mips/Kconfig
index af4e04fde0b483ad9979e25eca515a0ab633ba31,79ad1d09c255731e2eb7bff553fb495ae96c4a42..6fe9a188c49fb1c67e74de67782c737d54e82d81
--- 1/arch/mips/Kconfig
--- 2/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@@ -835,8 -863,9 +854,9 @@@ source "arch/mips/jazz/Kconfig
  source "arch/mips/jz4740/Kconfig"
  source "arch/mips/lantiq/Kconfig"
  source "arch/mips/lasat/Kconfig"
 -source "arch/mips/pmc-sierra/Kconfig"
 +source "arch/mips/pmcs-msp71xx/Kconfig"
  source "arch/mips/powertv/Kconfig"
+ source "arch/mips/ralink/Kconfig"
  source "arch/mips/sgi-ip27/Kconfig"
  source "arch/mips/sibyte/Kconfig"
  source "arch/mips/txx9/Kconfig"

diff --cc arch/mips/ath79/clock.c
Simple merge

diff --cc arch/mips/bcm47xx/nvram.c
index c37419c11c921a7fde30eaa42dace4fa47b820ec,e63bd5abd9a23359bb04be009c674533a1250ddf..cc40b74940f5f6531e4e74cfcf4c665a7b13a9fd
--- 1/arch/mips/bcm47xx/nvram.c
--- 2/arch/mips/bcm47xx/nvram.c
+++ b/arch/mips/bcm47xx/nvram.c
@@@ -3,10 -3,10 +3,10 @@@
   *
   * Copyright (C) 2005 Broadcom Corporation
   * Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
-  * Copyright (C) 2010-2011 Hauke Mehrtens <hauke@hauke-m.de>
+  * Copyright (C) 2010-2012 Hauke Mehrtens <hauke@hauke-m.de>
   *
 - * This program is free software; you can redistribute  it and/or modify it
 - * under  the terms of  the GNU General  Public License as published by the
 + * This program is free software; you can redistribute        it and/or modify it
 + * under  the terms of        the GNU General  Public License as published by the
   * Free Software Foundation;  either version 2 of the  License, or (at your
   * option) any later version.
   */

diff --cc arch/mips/bcm47xx/sprom.c
Simple merge

diff --cc arch/mips/include/asm/cpu-features.h
Simple merge

diff --cc arch/mips/include/asm/cpu.h
Simple merge

diff --cc arch/mips/include/asm/gic.h
Simple merge

diff --cc arch/mips/include/asm/hazards.h
Simple merge

diff --cc arch/mips/include/asm/mach-ath79/ar71xx_regs.h
index 8dec938af115153b88660a7ee3a2ba92c666deaa,4de183112917b8d3457915446af49746f9909913..b86a1253a5bf712af01fd988f95e9f8a16b4b582
--- 1/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
--- 2/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
+++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
@@@ -312,9 -396,11 +396,11 @@@
  #define AR934X_BOOTSTRAP_EJTAG_MODE   BIT(5)
  #define AR934X_BOOTSTRAP_REF_CLK_40   BIT(4)
  #define AR934X_BOOTSTRAP_BOOT_FROM_SPI        BIT(2)
 -#define AR934X_BOOTSTRAP_SDRAM_DISABLED       BIT(1)
 +#define AR934X_BOOTSTRAP_SDRAM_DISABLED BIT(1)
  #define AR934X_BOOTSTRAP_DDR1         BIT(0)
  
+ #define QCA955X_BOOTSTRAP_REF_CLK_40  BIT(4)
+ 
  #define AR934X_PCIE_WMAC_INT_WMAC_MISC                BIT(0)
  #define AR934X_PCIE_WMAC_INT_WMAC_TX          BIT(1)
  #define AR934X_PCIE_WMAC_INT_WMAC_RXLP                BIT(2)
@@@ -362,8 -481,10 +481,10 @@@
  
  #define AR724X_REV_ID_REVISION_MASK   0x3
  
 -#define AR934X_REV_ID_REVISION_MASK     0xf
 +#define AR934X_REV_ID_REVISION_MASK   0xf
  
+ #define QCA955X_REV_ID_REVISION_MASK  0xf
+ 
  /*
   * SPI block
   */

diff --cc arch/mips/include/asm/mips-boards/generic.h
index 1465b1193b12055c9cbe9770b29cbc3357b323ea,fa188ff08e5a42a2384d1e894a12980c35af077f..44a09a64160ac52fac8862beaaa8a9c9815f3fd2
--- 1/arch/mips/include/asm/mips-boards/generic.h
--- 2/arch/mips/include/asm/mips-boards/generic.h
+++ b/arch/mips/include/asm/mips-boards/generic.h
@@@ -27,16 -20,9 +20,9 @@@
  /*
   * Display register base.
   */
 -#define ASCII_DISPLAY_WORD_BASE    0x1f000410
 -#define ASCII_DISPLAY_POS_BASE     0x1f000418
 +#define ASCII_DISPLAY_WORD_BASE          0x1f000410
 +#define ASCII_DISPLAY_POS_BASE           0x1f000418
  
- 
- /*
-  * Yamon Prom print address.
-  */
- #define YAMON_PROM_PRINT_ADDR    0x1fc00504
- 
- 
  /*
   * Reset register.
   */

diff --cc arch/mips/include/asm/mipsregs.h
index 2145162674b9798cfbddcbe4d6e8b0a6f2894b06,5df4cda4991af8df1ba60dd08544d4b9d332f7ef..12b70c25906a0d3a32d095b52d3766bc2285e115
--- 1/arch/mips/include/asm/mipsregs.h
--- 2/arch/mips/include/asm/mipsregs.h
+++ b/arch/mips/include/asm/mipsregs.h
@@@ -1142,36 -1144,28 +1144,32 @@@ do {                                                                 
  /*
   * Macros to access the floating point coprocessor control registers
   */
 -#define read_32bit_cp1_register(source)                         \
 -({ int __res;                                                   \
 -      __asm__ __volatile__(                                   \
 -      ".set\tpush\n\t"                                        \
 -      ".set\treorder\n\t"                                     \
 -      /* gas fails to assemble cfc1 for some archs (octeon).*/ \
 -      ".set\tmips1\n\t"                                       \
 -        "cfc1\t%0,"STR(source)"\n\t"                            \
 -      ".set\tpop"                                             \
 -        : "=r" (__res));                                        \
 -        __res;})
 +#define read_32bit_cp1_register(source)                                       \
 +({                                                                    \
 +      int __res;                                                      \
 +                                                                      \
 +      __asm__ __volatile__(                                           \
 +      "       .set    push                                    \n"     \
 +      "       .set    reorder                                 \n"     \
 +      "       # gas fails to assemble cfc1 for some archs,    \n"     \
 +      "       # like Octeon.                                  \n"     \
 +      "       .set    mips1                                   \n"     \
 +      "       cfc1    %0,"STR(source)"                        \n"     \
 +      "       .set    pop                                     \n"     \
 +      : "=r" (__res));                                                \
 +      __res;                                                          \
 +})
  
+ #ifdef HAVE_AS_DSP
  #define rddsp(mask)                                                   \
  ({                                                                    \
-       unsigned int __res;                                             \
+       unsigned int __dspctl;                                          \
                                                                        \
        __asm__ __volatile__(                                           \
-       "       .set    push                            \n"             \
-       "       .set    noat                            \n"             \
-       "       # rddsp $1, %x1                         \n"             \
-       "       .word   0x7c000cb8 | (%x1 << 16)        \n"             \
-       "       move    %0, $1                          \n"             \
-       "       .set    pop                             \n"             \
-       : "=r" (__res)                                                  \
+       "       rddsp   %0, %x1                                 \n"     \
+       : "=r" (__dspctl)                                               \
        : "i" (mask));                                                  \
-       __res;                                                          \
+       __dspctl;                                                       \
  })
  
  #define wrdsp(val, mask)                                              \

diff --cc arch/mips/include/asm/netlogic/mips-extns.h
Simple merge

diff --cc arch/mips/include/asm/netlogic/xlp-hal/pic.h
Simple merge

diff --cc arch/mips/include/asm/netlogic/xlr/pic.h
Simple merge

diff --cc arch/mips/include/asm/pci.h
Simple merge

diff --cc arch/mips/include/asm/time.h
Simple merge

diff --cc arch/mips/kernel/Makefile
Simple merge

diff --cc arch/mips/kernel/cpu-probe.c
Simple merge

diff --cc arch/mips/kernel/irq_cpu.c
Simple merge

diff --cc arch/mips/kernel/proc.c
Simple merge

diff --cc arch/mips/kernel/setup.c
Simple merge

diff --cc arch/mips/kernel/smtc.c
Simple merge

diff --cc arch/mips/kernel/vpe.c
Simple merge

diff --cc arch/mips/lantiq/clk.c
Simple merge

diff --cc arch/mips/loongson1/common/prom.c
Simple merge

diff --cc arch/mips/mm/c-r4k.c
Simple merge

diff --cc arch/mips/mm/tlbex.c
Simple merge

diff --cc arch/mips/netlogic/common/irq.c
Simple merge

diff --cc arch/mips/netlogic/common/smpboot.S
Simple merge

diff --cc arch/mips/netlogic/xlr/fmn-config.c
Simple merge

diff --cc arch/mips/netlogic/xlr/platform.c
Simple merge

diff --cc arch/mips/netlogic/xlr/setup.c
Simple merge

diff --cc arch/mips/oprofile/common.c
Simple merge

diff --cc arch/mips/oprofile/op_model_mipsxx.c
Simple merge

diff --cc arch/mips/pci/pci-xlp.c
index ad55f2cfeec14d7ee35b11be37b1f3c2d00b96c3,dd2d3eb3ad31b68880b97e0c77095b82ce75f903..653d2db9e0c5187d516cf73e2e6268b375e481fd
--- 1/arch/mips/pci/pci-xlp.c
--- 2/arch/mips/pci/pci-xlp.c
+++ b/arch/mips/pci/pci-xlp.c
@@@ -149,35 -154,29 +154,29 @@@ static struct resource nlm_pci_io_resou
  };
  
  struct pci_controller nlm_pci_controller = {
 -      .index          = 0,
 -      .pci_ops        = &nlm_pci_ops,
 -      .mem_resource   = &nlm_pci_mem_resource,
 -      .mem_offset     = 0x00000000UL,
 -      .io_resource    = &nlm_pci_io_resource,
 -      .io_offset      = 0x00000000UL,
 +      .index          = 0,
 +      .pci_ops        = &nlm_pci_ops,
 +      .mem_resource   = &nlm_pci_mem_resource,
 +      .mem_offset     = 0x00000000UL,
 +      .io_resource    = &nlm_pci_io_resource,
 +      .io_offset      = 0x00000000UL,
  };
  
- static int get_irq_vector(const struct pci_dev *dev)
+ static struct pci_dev *xlp_get_pcie_link(const struct pci_dev *dev)
  {
-       /*
-        * For XLP PCIe, there is an IRQ per Link, find out which
-        * link the device is on to assign interrupts
-       */
-       if (dev->bus->self == NULL)
-               return 0;
+       struct pci_bus *bus, *p;
  
-       switch  (dev->bus->self->devfn) {
-       case 0x8:
-               return PIC_PCIE_LINK_0_IRQ;
-       case 0x9:
-               return PIC_PCIE_LINK_1_IRQ;
-       case 0xa:
-               return PIC_PCIE_LINK_2_IRQ;
-       case 0xb:
-               return PIC_PCIE_LINK_3_IRQ;
-       }
-       WARN(1, "Unexpected devfn %d\n", dev->bus->self->devfn);
-       return 0;
+       /* Find the bridge on bus 0 */
+       bus = dev->bus;
+       for (p = bus->parent; p && p->number != 0; p = p->parent)
+               bus = p;
+ 
+       return p ? bus->self : NULL;
+ }
+ 
+ static inline int nlm_pci_link_to_irq(int link)
+ {
+       return PIC_PCIE_LINK_0_IRQ + link;
  }
  
  int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
@@@ -232,10 -249,29 +249,29 @@@ static int __init pcibios_init(void
        pci_config_base = ioremap(XLP_DEFAULT_PCI_ECFG_BASE, 64 << 20);
  
        /* Extend IO port for memory mapped io */
 -      ioport_resource.start =  0;
 +      ioport_resource.start =  0;
        ioport_resource.end   = ~0;
  
-       xlp_enable_pci_bswap();
+       for (n = 0; n < NLM_NR_NODES; n++) {
+               nodep = nlm_get_node(n);
+               if (!nodep->coremask)
+                       continue;       /* node does not exist */
+ 
+               for (link = 0; link < 4; link++) {
+                       pciebase = nlm_get_pcie_base(n, link);
+                       if (nlm_read_pci_reg(pciebase, 0) == 0xffffffff)
+                               continue;
+                       xlp_config_pci_bswap(n, link);
+ 
+                       /* put in intpin and irq - u-boot does not */
+                       reg = nlm_read_pci_reg(pciebase, 0xf);
+                       reg &= ~0x1fu;
+                       reg |= (1 << 8) | nlm_pci_link_to_irq(link);
+                       nlm_write_pci_reg(pciebase, 0xf, reg);
+                       pr_info("XLP PCIe: Link %d-%d initialized.\n", n, link);
+               }
+       }
+ 
        set_io_port_base(CKSEG1);
        nlm_pci_controller.io_map_base = CKSEG1;
  

diff --cc arch/mips/pci/pci.c
Simple merge