drm/i915: Handle PipeC fused off on IVB/HSW/BDW

Some Gen7/8 production parts may have the Display Pipe C fused off.
In this case, the display hardware will prevent the enable bit in
PIPE_CONF register (for Pipe C) from being set to 1.

Fixed by adjusting pipe_count to reflect this.

v2: Rename HSW_PIPE_C_DISABLE to IVB_PIPE_C_DISABLE as it already exists
    on ivybridge (Ville)
v3: Remove unnecessary MMIO read, correct the description (Damien)
v4: Be more specific in description (Patrick)

Signed-off-by: Gabriel Feceoru <gabriel.feceoru@intel.com>
Reviewed-by: Patrik Jakobsson <patrik.jakobsson@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Link: http://patchwork.freedesktop.org/patch/msgid/1453462125-21519-1-git-send-email-gabriel.feceoru@intel.com

diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index a42eb58f7c4131feb29736b2bc92ab547d10f1a7..35c2b33560b4fd97ddc2318f1a05e70e54cd7c1d 100644 (file)
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -808,6 +808,9 @@ static void intel_device_info_runtime_init(struct drm_device *dev)
                     !(sfuse_strap & SFUSE_STRAP_FUSE_LOCK))) {
                        DRM_INFO("Display fused off, disabling\n");
                        info->num_pipes = 0;
+               } else if (fuse_strap & IVB_PIPE_C_DISABLE) {
+                       DRM_INFO("PipeC fused off\n");
+                       info->num_pipes -= 1;
                }
        } else if (info->num_pipes > 0 && INTEL_INFO(dev)->gen == 9) {
                u32 dfsm = I915_READ(SKL_DFSM);

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 665ae4846731ba819b6a0d044d412d1da79d9e23..144586ee74d5a510e55dd87c01c6d2fb201159a7 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5949,6 +5949,7 @@ enum skl_disp_power_wells {
 #define  ILK_INTERNAL_GRAPHICS_DISABLE (1 << 31)
 #define  ILK_INTERNAL_DISPLAY_DISABLE  (1 << 30)
 #define  ILK_DISPLAY_DEBUG_DISABLE     (1 << 29)
+#define  IVB_PIPE_C_DISABLE            (1 << 28)
 #define  ILK_HDCP_DISABLE              (1 << 25)
 #define  ILK_eDP_A_DISABLE             (1 << 24)
 #define  HSW_CDCLK_LIMIT               (1 << 24)